Unified Coverage Report :: Module :: prim_packer_fifo

Module : prim_packer_fifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.24	100.00

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	95.24

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T9,T49
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T115,T41,T206
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	90966368	8711127	0	7560
ValidOPairedWithReadyI_A	90966368	8711127	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90966368	8711127	0	7560
T1	939	788	0	1
T2	1178	987	0	1
T3	4104	1819	0	1
T4	1248	263	0	2
T5	1882	427	0	2
T6	23340	6610	0	1
T7	1329	0	0	1
T9	5112	1264	0	2
T10	2051	0	0	1
T14	23494	0	0	1
T17	0	1035	0	0
T22	2064	0	0	2
T23	4328	1321	0	2
T24	1758	0	0	2
T25	3854	1494	0	2
T26	1926	1492	0	1
T27	0	1162	0	0
T28	0	1472	0	0
T30	991	0	0	1
T39	6956	5415	0	2
T43	0	860	0	0
T44	0	993	0	0
T46	0	3470	0	0
T49	3098	0	0	1
T57	9324	6586	0	1
T62	849	637	0	1
T63	1663	0	0	1
T64	0	825	0	0
T70	0	659	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90966368	8711127	0	0
T1	939	788	0	0
T2	1178	987	0	0
T3	4104	1819	0	0
T4	1248	263	0	0
T5	1882	427	0	0
T6	23340	6610	0	0
T7	1329	0	0	0
T9	5112	1264	0	0
T10	2051	0	0	0
T14	23494	0	0	0
T17	0	1035	0	0
T22	2064	0	0	0
T23	4328	1321	0	0
T24	1758	0	0	0
T25	3854	1494	0	0
T26	1926	1492	0	0
T27	0	1162	0	0
T28	0	1472	0	0
T30	991	0	0	0
T39	6956	5415	0	0
T43	0	860	0	0
T44	0	993	0	0
T46	0	3470	0	0
T49	3098	0	0	0
T57	9324	6586	0	0
T62	849	637	0	0
T63	1663	0	0	0
T64	0	825	0	0
T70	0	659	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T9,T49
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
Branches		14	12	85.71
TERNARY	142	4	3	75.00
TERNARY	147	3	2	66.67
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	166751	0	945
ValidOPairedWithReadyI_A	11370796	166751	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	166751	0	945
T3	4104	21	0	1
T4	624	14	0	1
T5	941	0	0	1
T6	23340	0	0	1
T9	2556	683	0	1
T10	0	83	0	0
T17	0	495	0	0
T22	1032	0	0	1
T23	2164	0	0	1
T24	879	0	0	1
T25	1927	0	0	1
T26	1926	0	0	1
T28	0	119	0	0
T29	0	14	0	0
T30	0	45	0	0
T39	0	73	0	0
T49	0	691	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	166751	0	0
T3	4104	21	0	0
T4	624	14	0	0
T5	941	0	0	0
T6	23340	0	0	0
T9	2556	683	0	0
T10	0	83	0	0
T17	0	495	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T28	0	119	0	0
T29	0	14	0	0
T30	0	45	0	0
T39	0	73	0	0
T49	0	691	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T115,T206,T72
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	7482199	0	945
ValidOPairedWithReadyI_A	11370796	7482199	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	7482199	0	945
T1	939	788	0	1
T2	1178	987	0	1
T3	4104	1819	0	1
T4	624	0	0	1
T5	941	427	0	1
T6	0	6610	0	0
T9	2556	0	0	1
T22	1032	0	0	1
T23	2164	0	0	1
T24	879	0	0	1
T25	1927	1494	0	1
T26	0	1492	0	0
T27	0	1162	0	0
T57	0	6586	0	0
T64	0	825	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	7482199	0	0
T1	939	788	0	0
T2	1178	987	0	0
T3	4104	1819	0	0
T4	624	0	0	0
T5	941	427	0	0
T6	0	6610	0	0
T9	2556	0	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	1494	0	0
T26	0	1492	0	0
T27	0	1162	0	0
T57	0	6586	0	0
T64	0	825	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T9,T39

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T23,T9,T39
1	0	Covered	T4,T23,T9
1	1	Covered	T23,T9,T39

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T9,T39

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T23,T9

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T23,T9
1	1	Covered	T4,T23,T9

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T23,T9

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T23,T9

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T23,T9

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T23,T9

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T221,T222
1	1	Covered	T4,T23,T9

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T4,T23,T9
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T23,T9
0	0	1	Covered	T4,T23,T9
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T23,T9
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T23,T9
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	215139	0	945
ValidOPairedWithReadyI_A	11370796	215139	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	215139	0	945
T4	624	263	0	1
T5	941	0	0	1
T6	23340	0	0	1
T9	2556	1264	0	1
T22	1032	0	0	1
T23	2164	1321	0	1
T24	879	0	0	1
T25	1927	0	0	1
T26	1926	0	0	1
T28	0	1472	0	0
T39	3478	2565	0	1
T43	0	860	0	0
T44	0	993	0	0
T46	0	1654	0	0
T62	0	637	0	0
T70	0	659	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	215139	0	0
T4	624	263	0	0
T5	941	0	0	0
T6	23340	0	0	0
T9	2556	1264	0	0
T22	1032	0	0	0
T23	2164	1321	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T28	0	1472	0	0
T39	3478	2565	0	0
T43	0	860	0	0
T44	0	993	0	0
T46	0	1654	0	0
T62	0	637	0	0
T70	0	659	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T17,T45

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T17,T45
1	0	Covered	T39,T17,T45
1	1	Covered	T39,T17,T45

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T17,T45

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T39,T17,T45

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T39,T17,T45
1	1	Covered	T39,T17,T45

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T17,T45

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T17,T45

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T17,T45

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T17,T45

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T17,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T223,T142,T165
1	1	Covered	T39,T17,T45

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T39,T17,T45
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T39,T17,T45
0	0	1	Covered	T39,T17,T45
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T17,T45
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T17,T45
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	188455	0	945
ValidOPairedWithReadyI_A	11370796	188455	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	188455	0	945
T7	1329	0	0	1
T10	2051	0	0	1
T11	0	1019	0	0
T14	23494	0	0	1
T17	0	1035	0	0
T30	991	0	0	1
T39	3478	2850	0	1
T42	0	1521	0	0
T45	0	842	0	0
T46	0	1816	0	0
T49	3098	0	0	1
T53	0	2124	0	0
T57	9324	0	0	1
T62	849	0	0	1
T63	1663	0	0	1
T64	1070	0	0	1
T73	0	832	0	0
T74	0	1639	0	0
T75	0	1009	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	188455	0	0
T7	1329	0	0	0
T10	2051	0	0	0
T11	0	1019	0	0
T14	23494	0	0	0
T17	0	1035	0	0
T30	991	0	0	0
T39	3478	2850	0	0
T42	0	1521	0	0
T45	0	842	0	0
T46	0	1816	0	0
T49	3098	0	0	0
T53	0	2124	0	0
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T73	0	832	0	0
T74	0	1639	0	0
T75	0	1009	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T49,T40

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T49,T40
1	0	Covered	T39,T7,T49
1	1	Covered	T39,T49,T40

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T49,T40

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T39,T7,T49

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T39,T7,T49
1	1	Covered	T39,T7,T49

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T7,T49

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T7,T49

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T7,T49

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T7,T49

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T7,T49
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T79,T171
1	1	Covered	T39,T7,T49

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T39,T7,T49
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T39,T7,T49
0	0	1	Covered	T39,T7,T49
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T7,T49
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T7,T49
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	202483	0	945
ValidOPairedWithReadyI_A	11370796	202483	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	202483	0	945
T7	1329	637	0	1
T10	2051	0	0	1
T14	23494	0	0	1
T30	991	0	0	1
T39	3478	2646	0	1
T40	0	1493	0	0
T46	0	1786	0	0
T48	0	778	0	0
T49	3098	1201	0	1
T50	0	62	0	0
T57	9324	0	0	1
T62	849	0	0	1
T63	1663	0	0	1
T64	1070	0	0	1
T68	0	1097	0	0
T78	0	891	0	0
T79	0	69	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	202483	0	0
T7	1329	637	0	0
T10	2051	0	0	0
T14	23494	0	0	0
T30	991	0	0	0
T39	3478	2646	0	0
T40	0	1493	0	0
T46	0	1786	0	0
T48	0	778	0	0
T49	3098	1201	0	0
T50	0	62	0	0
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T68	0	1097	0	0
T78	0	891	0	0
T79	0	69	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T51,T44

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T51,T44
1	0	Covered	T30,T40,T51
1	1	Covered	T40,T51,T44

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T51,T44

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T40,T51

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T40,T51
1	1	Covered	T30,T40,T51

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T40,T51

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T40,T51

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T40,T51

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T40,T51

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T40,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T224,T225
1	1	Covered	T30,T40,T51

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T30,T40,T51
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T30,T40,T51
0	0	1	Covered	T30,T40,T51
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T30,T40,T51
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T30,T40,T51
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	168625	0	945
ValidOPairedWithReadyI_A	11370796	168625	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	168625	0	945
T7	1329	0	0	1
T10	2051	0	0	1
T14	23494	0	0	1
T27	1544	0	0	1
T30	991	416	0	1
T31	0	170	0	0
T40	0	2195	0	0
T44	0	111	0	0
T46	0	1756	0	0
T49	3098	0	0	1
T51	0	717	0	0
T52	0	363	0	0
T53	0	1939	0	0
T57	9324	0	0	1
T62	849	0	0	1
T63	1663	0	0	1
T64	1070	0	0	1
T83	0	1044	0	0
T84	0	729	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	168625	0	0
T7	1329	0	0	0
T10	2051	0	0	0
T14	23494	0	0	0
T27	1544	0	0	0
T30	991	416	0	0
T31	0	170	0	0
T40	0	2195	0	0
T44	0	111	0	0
T46	0	1756	0	0
T49	3098	0	0	0
T51	0	717	0	0
T52	0	363	0	0
T53	0	1939	0	0
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T83	0	1044	0	0
T84	0	729	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T54,T46

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T54,T46
1	0	Covered	T22,T40,T54
1	1	Covered	T40,T54,T46

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T54,T46

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T22,T40,T54

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T40,T54
1	1	Covered	T22,T40,T54

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T40,T54

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T40,T54

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T40,T54

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T40,T54

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T40,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T87,T88
1	1	Covered	T22,T40,T54

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T22,T40,T54
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T22,T40,T54
0	0	1	Covered	T22,T40,T54
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T22,T40,T54
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T22,T40,T54
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	148251	0	945
ValidOPairedWithReadyI_A	11370796	148251	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	148251	0	945
T5	941	0	0	1
T6	23340	0	0	1
T9	2556	0	0	1
T20	0	945	0	0
T22	1032	819	0	1
T23	2164	0	0	1
T24	879	0	0	1
T25	1927	0	0	1
T26	1926	0	0	1
T30	991	0	0	1
T39	3478	0	0	1
T40	0	1581	0	0
T46	0	1748	0	0
T53	0	2086	0	0
T54	0	617	0	0
T87	0	569	0	0
T88	0	116	0	0
T89	0	389	0	0
T90	0	1427	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	148251	0	0
T5	941	0	0	0
T6	23340	0	0	0
T9	2556	0	0	0
T20	0	945	0	0
T22	1032	819	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T30	991	0	0	0
T39	3478	0	0	0
T40	0	1581	0	0
T46	0	1748	0	0
T53	0	2086	0	0
T54	0	617	0	0
T87	0	569	0	0
T88	0	116	0	0
T89	0	389	0	0
T90	0	1427	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T10,T40

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T10,T40
1	0	Covered	T39,T10,T40
1	1	Covered	T39,T10,T40

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T10,T40

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T39,T10,T40

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T39,T10,T40
1	1	Covered	T39,T10,T40

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T10,T40

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T10,T40

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T10,T40

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T10,T40

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T10,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T173,T217
1	1	Covered	T39,T10,T40

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T39,T10,T40
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T39,T10,T40
0	0	1	Covered	T39,T10,T40
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T10,T40
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T10,T40
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11370796	139224	0	945
ValidOPairedWithReadyI_A	11370796	139224	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	139224	0	945
T7	1329	0	0	1
T10	2051	945	0	1
T14	23494	0	0	1
T21	0	600	0	0
T30	991	0	0	1
T34	0	495	0	0
T39	3478	2488	0	1
T40	0	1376	0	0
T46	0	1529	0	0
T49	3098	0	0	1
T57	9324	0	0	1
T59	0	1103	0	0
T62	849	0	0	1
T63	1663	0	0	1
T64	1070	0	0	1
T91	0	735	0	0
T92	0	790	0	0
T93	0	705	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	139224	0	0
T7	1329	0	0	0
T10	2051	945	0	0
T14	23494	0	0	0
T21	0	600	0	0
T30	991	0	0	0
T34	0	495	0	0
T39	3478	2488	0	0
T40	0	1376	0	0
T46	0	1529	0	0
T49	3098	0	0	0
T57	9324	0	0	0
T59	0	1103	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T91	0	735	0	0
T92	0	790	0	0
T93	0	705	0	0