Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.21 98.25 93.97 97.02 91.86 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 94.13 99.92 92.75 82.54 91.86 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT28,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT4,T5,T6

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T5,T28 Yes T2,T5,T28 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T2,T10,T4 Yes T2,T10,T4 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T36,T37,T38 Yes T36,T37,T38 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T10,T4,T21 Yes T1,T10,T4 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[1].edn_req Yes Yes T22,T26,T39 Yes T22,T26,T39 INPUT
edn_i[2].edn_req Yes Yes T10,T5,T26 Yes T10,T5,T26 INPUT
edn_i[3].edn_req Yes Yes T10,T40,T30 Yes T10,T40,T30 INPUT
edn_i[4].edn_req Yes Yes T10,T13,T19 Yes T10,T13,T19 INPUT
edn_i[5].edn_req Yes Yes T10,T41,T42 Yes T10,T41,T42 INPUT
edn_i[6].edn_req Yes Yes T10,T27,T30 Yes T10,T27,T30 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T10,T9,T24 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_fips Yes Yes T10,T4,T6 Yes T1,T3,T10 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T22,T26,T39 Yes T22,T26,T39 OUTPUT
edn_o[1].edn_fips Yes Yes T43,T44,T45 Yes T43,T44,T46 OUTPUT
edn_o[1].edn_ack Yes Yes T22,T26,T39 Yes T22,T26,T39 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T10,T26,T29 Yes T10,T26,T29 OUTPUT
edn_o[2].edn_fips Yes Yes T26,T44,T47 Yes T10,T26,T29 OUTPUT
edn_o[2].edn_ack Yes Yes T10,T26,T29 Yes T10,T26,T29 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T10,T40,T43 Yes T10,T40,T43 OUTPUT
edn_o[3].edn_fips Yes Yes T10,T40,T43 Yes T10,T40,T43 OUTPUT
edn_o[3].edn_ack Yes Yes T10,T40,T30 Yes T10,T40,T30 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T10,T48,T43 Yes T10,T13,T19 OUTPUT
edn_o[4].edn_fips Yes Yes T49,T50,T51 Yes T13,T52,T49 OUTPUT
edn_o[4].edn_ack Yes Yes T10,T13,T19 Yes T10,T13,T19 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T10,T41,T42 Yes T10,T41,T42 OUTPUT
edn_o[5].edn_fips Yes Yes T10,T53,T45 Yes T10,T44,T53 OUTPUT
edn_o[5].edn_ack Yes Yes T10,T41,T42 Yes T10,T41,T42 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T10,T27,T30 Yes T10,T27,T30 OUTPUT
edn_o[6].edn_fips Yes Yes T10,T30,T54 Yes T10,T27,T30 OUTPUT
edn_o[6].edn_ack Yes Yes T10,T27,T30 Yes T10,T27,T30 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T10,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T10,T9,T22 Yes T10,T9,T28 INPUT
csrng_cmd_i.genbits_fips Yes Yes T10,T26,T13 Yes T10,T22,T26 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T21,T28,T29 Yes T21,T28,T29 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T4,T21,T5 Yes T4,T21,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T21,T28,T29 Yes T21,T28,T29 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T4,T21,T5 Yes T4,T21,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T58,T59,T60 Yes T58,T59,T60 OUTPUT
intr_edn_fatal_err_o Yes Yes T4,T6,T61 Yes T4,T6,T61 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 11155850 10981157 0 0
CsrngAppIfOut_A 11155850 10981157 0 0
FpvSecCmCntAlertCheck_A 11155850 105 0 0
FpvSecCmGenCmdFifoRptrCheck_A 11155850 70 0 0
FpvSecCmGenCmdFifoWptrCheck_A 11155850 70 0 0
FpvSecCmMainFsmCheck_A 11155850 70 0 0
FpvSecCmRegWeOnehotCheck_A 11155850 70 0 0
FpvSecCmResCmdFifoRptrCheck_A 11155850 70 0 0
FpvSecCmResCmdFifoWptrCheck_A 11155850 70 0 0
IntrEdnCmdReqDoneKnownO_A 11155850 10981157 0 0
TlAReadyKnownO_A 11155850 10981157 0 0
TlDValidKnownO_A 11155850 10981157 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 11155850 70 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[0].EdnDataStable_A 11155850 20365 0 430
gen_edn_if_asserts[0].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[1].EdnDataStable_A 11155850 5849 0 143
gen_edn_if_asserts[1].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[2].EdnDataStable_A 11155850 5136 0 122
gen_edn_if_asserts[2].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[3].EdnDataStable_A 11155850 4642 0 110
gen_edn_if_asserts[3].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[4].EdnDataStable_A 11155850 3850 0 107
gen_edn_if_asserts[4].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[5].EdnDataStable_A 11155850 1604 0 81
gen_edn_if_asserts[5].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 11155850 149210 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 11155850 570398 0 284
gen_edn_if_asserts[6].EdnDataStable_A 11155850 2315 0 95
gen_edn_if_asserts[6].EdnEndPointOut_A 11155850 10981157 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 11155850 149210 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 105 0 0
T14 1988 1 0 0
T15 0 1 0 0
T16 0 10 0 0
T17 0 20 0 0
T18 0 10 0 0
T53 0 1 0 0
T59 19726 0 0 0
T60 11637 0 0 0
T62 0 1 0 0
T63 0 10 0 0
T64 0 20 0 0
T65 0 1 0 0
T66 1041 0 0 0
T67 1583 0 0 0
T68 1086 0 0 0
T69 1295 0 0 0
T70 1267 0 0 0
T71 1530 0 0 0
T72 3815 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 70 0 0
T16 22931 10 0 0
T17 46323 20 0 0
T18 0 10 0 0
T20 1720 0 0 0
T52 721 0 0 0
T63 0 10 0 0
T64 0 20 0 0
T73 831 0 0 0
T74 2010 0 0 0
T75 2458 0 0 0
T76 832 0 0 0
T77 838 0 0 0
T78 1486 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 20365 0 430
T1 1342 3 0 1
T2 1070 3 0 1
T3 2960 3 0 1
T4 1389 1 0 0
T5 1188 0 0 0
T9 2407 4 0 0
T10 3300 37 0 1
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 3 0 1
T24 0 3 0 1
T25 0 0 0 1
T26 0 3 0 1
T28 0 4 0 1
T81 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 5849 0 143
T6 713 0 0 0
T22 1287 4 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 3 0 1
T27 1142 0 0 0
T28 1763 0 0 0
T29 3024 0 0 0
T39 3241 7 0 1
T43 0 64 0 1
T44 0 40 0 1
T45 0 40 0 1
T46 0 3 0 1
T51 0 0 0 1
T54 0 4 0 1
T81 901 0 0 0
T82 0 3 0 1
T83 0 4 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 5136 0 122
T4 1389 0 0 0
T5 1188 0 0 0
T9 2407 0 0 0
T10 3300 4 0 1
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 23 0 1
T28 1763 0 0 0
T29 0 4 0 1
T43 0 3 0 1
T44 0 25 0 1
T45 0 0 0 1
T47 0 0 0 1
T73 0 3 0 1
T75 0 4 0 1
T84 0 3 0 1
T85 0 4 0 0
T86 0 4 0 0

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 4642 0 110
T4 1389 0 0 0
T5 1188 0 0 0
T9 2407 0 0 0
T10 3300 111 0 1
T20 0 4 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T30 0 4 0 1
T32 0 1 0 0
T40 0 4 0 0
T43 0 45 0 1
T45 0 0 0 1
T47 0 0 0 1
T50 0 0 0 1
T51 0 0 0 1
T87 0 44 0 1
T88 0 1 0 0
T89 0 4 0 0
T90 0 1 0 0
T91 0 0 0 1
T92 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 3850 0 107
T4 1389 0 0 0
T5 1188 0 0 0
T9 2407 0 0 0
T10 3300 15 0 1
T13 0 4 0 0
T19 0 4 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T35 0 1 0 0
T43 0 3 0 1
T45 0 0 0 1
T47 0 0 0 1
T48 0 3 0 1
T49 0 4 0 0
T50 0 0 0 1
T51 0 0 0 1
T52 0 3 0 1
T89 0 4 0 1
T93 0 1 0 0
T94 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 1604 0 81
T4 1389 0 0 0
T5 1188 0 0 0
T9 2407 0 0 0
T10 3300 40 0 1
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 1 0 0
T42 0 5 0 0
T44 0 8 0 1
T45 0 50 0 1
T47 0 3 0 1
T53 0 1 0 0
T91 0 13 0 1
T95 0 3 0 1
T96 0 4 0 0
T97 0 0 0 1
T98 0 0 0 1
T99 0 0 0 1
T100 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 570398 0 284
T1 1342 28 0 0
T2 1070 12 0 0
T3 2960 19 0 0
T4 1389 552 0 0
T5 1188 697 0 0
T9 2407 1536 0 2
T10 3300 61 0 0
T13 0 0 0 2
T19 0 0 0 2
T21 1128 1063 0 2
T22 1287 82 0 0
T23 1146 27 0 0
T58 0 0 0 2
T59 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T79 0 0 0 2
T80 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 2315 0 95
T4 1389 0 0 0
T5 1188 0 0 0
T9 2407 0 0 0
T10 3300 53 0 1
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T27 0 3 0 1
T28 1763 0 0 0
T30 0 4 0 0
T54 0 4 0 0
T67 0 4 0 0
T88 0 4 0 0
T98 0 0 0 1
T101 0 4 0 0
T102 0 4 0 0
T103 0 3 0 1
T104 0 1 0 0
T105 0 0 0 1
T106 0 0 0 1
T107 0 0 0 1
T108 0 0 0 1
T109 0 0 0 1
T110 0 0 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 10981157 0 0
T1 1342 1244 0 0
T2 1070 984 0 0
T3 2960 2873 0 0
T4 1389 1256 0 0
T5 1188 1047 0 0
T9 2407 2355 0 0
T10 3300 3234 0 0
T21 1128 1065 0 0
T22 1287 1202 0 0
T23 1146 1075 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11155850 149210 0 0
T4 1389 646 0 0
T5 1188 375 0 0
T6 713 7 0 0
T7 0 379 0 0
T8 0 682 0 0
T9 2407 0 0 0
T14 0 1104 0 0
T15 0 632 0 0
T21 1128 0 0 0
T22 1287 0 0 0
T23 1146 0 0 0
T24 1120 0 0 0
T26 2402 0 0 0
T28 1763 0 0 0
T41 0 610 0 0
T61 0 1110 0 0
T69 0 609 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%