Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11649615	386325	0	0
boot_gen_cmd_rd_A	11649615	3387	0	0
boot_ins_cmd_rd_A	11649615	3814	0	0
ctrl_rd_A	11649615	3678	0	0
err_code_test_rd_A	11649615	3600	0	0
intr_enable_rd_A	11649615	7625	0	0
max_num_reqs_between_reseeds_rd_A	11649615	4140	0	0
regwen_rd_A	11649615	4656	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	386325	0	0
T36	55468	4341	0	0
T37	61694	5009	0	0
T38	0	8637	0	0
T96	2268	0	0	0
T105	971	0	0	0
T157	2212	0	0	0
T238	0	5498	0	0
T239	0	8248	0	0
T240	0	5512	0	0
T241	0	6836	0	0
T242	0	7682	0	0
T243	0	13178	0	0
T244	0	5995	0	0
T245	448	0	0	0
T246	789	0	0	0
T247	9276	0	0	0
T248	1716	0	0	0
T249	1305	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	3387	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	183	0	0
T243	0	430	0	0
T250	0	559	0	0
T251	0	513	0	0
T252	0	86	0	0
T253	0	54	0	0
T254	0	254	0	0
T255	0	544	0	0
T256	0	177	0	0
T257	0	282	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	0	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	3814	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	193	0	0
T243	0	480	0	0
T250	0	495	0	0
T251	0	537	0	0
T252	0	137	0	0
T253	0	58	0	0
T254	0	336	0	0
T255	0	546	0	0
T256	0	358	0	0
T257	0	346	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	0	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	3678	0	0
T1	1342	9	0	0
T2	1070	0	0	0
T3	2960	1	0	0
T4	1389	7	0	0
T5	1188	0	0	0
T9	2407	0	0	0
T10	3300	0	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T25	0	3	0	0
T70	0	9	0	0
T240	0	214	0	0
T258	0	1	0	0
T265	0	3	0	0
T266	0	4	0	0
T267	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	3600	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	163	0	0
T243	0	486	0	0
T250	0	573	0	0
T251	0	481	0	0
T252	0	159	0	0
T253	0	47	0	0
T254	0	262	0	0
T255	0	537	0	0
T256	0	329	0	0
T257	0	295	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	0	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	7625	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	438	0	0
T243	0	794	0	0
T250	0	735	0	0
T251	0	854	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	52	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0
T268	0	7	0	0
T269	0	57	0	0
T270	0	29	0	0
T271	0	22	0	0
T272	0	24	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	4140	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	155	0	0
T243	0	431	0	0
T250	0	586	0	0
T251	0	426	0	0
T252	0	110	0	0
T253	0	64	0	0
T254	0	245	0	0
T255	0	505	0	0
T256	0	205	0	0
T257	0	256	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	0	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11649615	4656	0	0
T233	3091	0	0	0
T236	1985	0	0	0
T240	161816	177	0	0
T243	0	460	0	0
T250	0	569	0	0
T251	0	555	0	0
T252	0	176	0	0
T253	0	73	0	0
T254	0	255	0	0
T255	0	606	0	0
T256	0	269	0	0
T257	0	276	0	0
T258	1156	0	0	0
T259	1826	0	0	0
T260	4116	0	0	0
T261	19425	0	0	0
T262	1063	0	0	0
T263	2029	0	0	0
T264	1081	0	0	0