Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12008204	414584	0	0
boot_gen_cmd_rd_A	12008204	3372	0	0
boot_ins_cmd_rd_A	12008204	3534	0	0
ctrl_rd_A	12008204	3358	0	0
err_code_test_rd_A	12008204	3472	0	0
intr_enable_rd_A	12008204	7879	0	0
max_num_reqs_between_reseeds_rd_A	12008204	4693	0	0
regwen_rd_A	12008204	4981	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	414584	0	0
T38	71177	3377	0	0
T39	0	11200	0	0
T40	0	10203	0	0
T57	2242	0	0	0
T101	1202	0	0	0
T102	1859	0	0	0
T168	2871	0	0	0
T192	1172	0	0	0
T233	0	11359	0	0
T234	0	8486	0	0
T235	0	6501	0	0
T236	0	5542	0	0
T237	0	10825	0	0
T238	0	9739	0	0
T239	0	13802	0	0
T240	2373	0	0	0
T241	1249	0	0	0
T242	1970	0	0	0
T243	2992	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	3372	0	0
T98	1935	0	0	0
T221	1151	0	0	0
T234	236610	331	0	0
T236	0	160	0	0
T237	0	323	0	0
T244	0	186	0	0
T245	0	218	0	0
T246	0	489	0	0
T247	0	390	0	0
T248	0	419	0	0
T249	0	496	0	0
T250	0	13	0	0
T251	1818	0	0	0
T252	1486	0	0	0
T253	1436	0	0	0
T254	22137	0	0	0
T255	1849	0	0	0
T256	1810	0	0	0
T257	2064	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	3534	0	0
T98	1935	0	0	0
T221	1151	0	0	0
T234	236610	319	0	0
T236	0	140	0	0
T237	0	343	0	0
T244	0	239	0	0
T245	0	272	0	0
T246	0	560	0	0
T247	0	433	0	0
T248	0	414	0	0
T249	0	407	0	0
T251	1818	0	0	0
T252	1486	0	0	0
T253	1436	0	0	0
T254	22137	0	0	0
T255	1849	0	0	0
T256	1810	0	0	0
T257	2064	0	0	0
T258	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	3358	0	0
T6	20548	0	0	0
T7	2551	0	0	0
T11	3833	0	0	0
T12	2824	0	0	0
T26	1783	6	0	0
T28	631	0	0	0
T33	1483	0	0	0
T64	12355	2	0	0
T65	0	8	0	0
T74	0	7	0	0
T75	1232	0	0	0
T77	1045	0	0	0
T117	0	1	0	0
T141	0	2	0	0
T170	0	4	0	0
T242	0	14	0	0
T259	0	3	0	0
T260	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	3472	0	0
T98	1935	0	0	0
T221	1151	0	0	0
T234	236610	355	0	0
T236	0	184	0	0
T237	0	398	0	0
T244	0	239	0	0
T245	0	202	0	0
T246	0	584	0	0
T247	0	488	0	0
T248	0	334	0	0
T249	0	393	0	0
T251	1818	0	0	0
T252	1486	0	0	0
T253	1436	0	0	0
T254	22137	0	0	0
T255	1849	0	0	0
T256	1810	0	0	0
T257	2064	0	0	0
T258	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	7879	0	0
T7	2551	0	0	0
T16	23702	0	0	0
T20	2259	0	0	0
T27	995	0	0	0
T29	677	0	0	0
T64	12355	85	0	0
T71	2164	0	0	0
T75	1232	0	0	0
T77	1045	0	0	0
T94	1360	0	0	0
T116	0	52	0	0
T117	0	37	0	0
T119	0	88	0	0
T120	0	23	0	0
T234	0	446	0	0
T236	0	214	0	0
T237	0	821	0	0
T261	0	20	0	0
T262	0	25	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	4693	0	0
T98	1935	0	0	0
T221	1151	0	0	0
T234	236610	301	0	0
T236	0	142	0	0
T237	0	350	0	0
T244	0	223	0	0
T245	0	168	0	0
T246	0	600	0	0
T247	0	408	0	0
T248	0	386	0	0
T249	0	452	0	0
T251	1818	0	0	0
T252	1486	0	0	0
T253	1436	0	0	0
T254	22137	0	0	0
T255	1849	0	0	0
T256	1810	0	0	0
T257	2064	0	0	0
T258	0	3	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12008204	4981	0	0
T98	1935	0	0	0
T221	1151	0	0	0
T234	236610	362	0	0
T236	0	139	0	0
T237	0	360	0	0
T244	0	237	0	0
T245	0	174	0	0
T246	0	653	0	0
T247	0	450	0	0
T248	0	368	0	0
T249	0	487	0	0
T251	1818	0	0	0
T252	1486	0	0	0
T253	1436	0	0	0
T254	22137	0	0	0
T255	1849	0	0	0
T256	1810	0	0	0
T257	2064	0	0	0
T258	0	9	0	0