Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.07 98.25 93.73 97.02 91.28 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 93.98 99.92 92.41 82.54 91.28 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT17,T12,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T18,T19
10CoveredT4,T5,T33

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T23,T25 Yes T2,T23,T25 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T2,T23,T4 Yes T2,T23,T5 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T23,T4 Yes T1,T2,T23 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[1].edn_req Yes Yes T5,T33,T12 Yes T5,T33,T12 INPUT
edn_i[2].edn_req Yes Yes T10,T16,T18 Yes T10,T16,T18 INPUT
edn_i[3].edn_req Yes Yes T23,T20,T16 Yes T23,T20,T16 INPUT
edn_i[4].edn_req Yes Yes T28,T7,T16 Yes T28,T7,T16 INPUT
edn_i[5].edn_req Yes Yes T16,T18,T21 Yes T16,T18,T21 INPUT
edn_i[6].edn_req Yes Yes T20,T16,T41 Yes T20,T16,T41 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_fips Yes Yes T3,T17,T6 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T5,T12,T42 Yes T5,T12,T42 OUTPUT
edn_o[1].edn_fips Yes Yes T5,T43,T44 Yes T5,T42,T43 OUTPUT
edn_o[1].edn_ack Yes Yes T5,T33,T12 Yes T5,T33,T12 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T45,T46,T43 Yes T10,T45,T46 OUTPUT
edn_o[2].edn_fips Yes Yes T47,T48,T49 Yes T43,T50,T47 OUTPUT
edn_o[2].edn_ack Yes Yes T10,T45,T46 Yes T10,T45,T46 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T51,T43,T52 Yes T23,T51,T43 OUTPUT
edn_o[3].edn_fips Yes Yes T53,T13,T54 Yes T23,T20,T43 OUTPUT
edn_o[3].edn_ack Yes Yes T23,T20,T51 Yes T23,T20,T51 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T29,T55,T56 Yes T29,T55,T43 OUTPUT
edn_o[4].edn_fips Yes Yes T7,T49,T57 Yes T7,T29,T55 OUTPUT
edn_o[4].edn_ack Yes Yes T28,T7,T29 Yes T28,T7,T29 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T43,T13,T58 Yes T21,T43,T13 OUTPUT
edn_o[5].edn_fips Yes Yes T43,T13,T58 Yes T43,T13,T58 OUTPUT
edn_o[5].edn_ack Yes Yes T21,T43,T13 Yes T21,T43,T13 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T20,T41,T59 Yes T20,T41,T59 OUTPUT
edn_o[6].edn_fips Yes Yes T60,T61,T62 Yes T41,T43,T63 OUTPUT
edn_o[6].edn_ack Yes Yes T20,T41,T59 Yes T20,T41,T59 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T23,T5 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T3,T64,T20 Yes T3,T11,T64 INPUT
csrng_cmd_i.genbits_fips Yes Yes T3,T11,T20 Yes T3,T10,T11 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T12,T45,T65 Yes T12,T45,T65 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T17,T24,T12 Yes T17,T24,T12 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T4,T5,T24 Yes T4,T5,T24 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T17,T24,T12 Yes T17,T24,T12 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T4,T5,T24 Yes T4,T5,T24 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T6,T64,T66 Yes T6,T64,T66 OUTPUT
intr_edn_fatal_err_o Yes Yes T5,T6,T33 Yes T5,T6,T33 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 11489854 11310599 0 0
CsrngAppIfOut_A 11489854 11310599 0 0
FpvSecCmCntAlertCheck_A 11489854 111 0 0
FpvSecCmGenCmdFifoRptrCheck_A 11489854 70 0 0
FpvSecCmGenCmdFifoWptrCheck_A 11489854 70 0 0
FpvSecCmMainFsmCheck_A 11489854 70 0 0
FpvSecCmRegWeOnehotCheck_A 11489854 70 0 0
FpvSecCmResCmdFifoRptrCheck_A 11489854 70 0 0
FpvSecCmResCmdFifoWptrCheck_A 11489854 70 0 0
IntrEdnCmdReqDoneKnownO_A 11489854 11310599 0 0
TlAReadyKnownO_A 11489854 11310599 0 0
TlDValidKnownO_A 11489854 11310599 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 11489854 70 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[0].EdnDataStable_A 11489854 16845 0 418
gen_edn_if_asserts[0].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[1].EdnDataStable_A 11489854 3149 0 130
gen_edn_if_asserts[1].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[2].EdnDataStable_A 11489854 2793 0 124
gen_edn_if_asserts[2].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[3].EdnDataStable_A 11489854 3484 0 100
gen_edn_if_asserts[3].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[4].EdnDataStable_A 11489854 2764 0 89
gen_edn_if_asserts[4].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[5].EdnDataStable_A 11489854 4477 0 83
gen_edn_if_asserts[5].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 11489854 154865 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 11489854 538088 0 296
gen_edn_if_asserts[6].EdnDataStable_A 11489854 2014 0 73
gen_edn_if_asserts[6].EdnEndPointOut_A 11489854 11310599 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 11489854 154865 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 111 0 0
T4 552 1 0 0
T5 2236 0 0 0
T6 20548 0 0 0
T7 0 1 0 0
T8 0 1 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 10 0 0
T17 2935 0 0 0
T18 0 10 0 0
T19 0 20 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T33 1483 0 0 0
T67 0 10 0 0
T68 0 1 0 0
T69 0 20 0 0
T70 0 1 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 70 0 0
T8 1811 0 0 0
T16 23702 10 0 0
T18 0 10 0 0
T19 0 20 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 0 0 0
T66 10776 0 0 0
T67 0 10 0 0
T69 0 20 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T73 949 0 0 0
T74 1264 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 16845 0 418
T1 1123 3 0 1
T2 1591 3 0 1
T3 2549 25 0 1
T4 552 0 0 0
T5 2236 0 0 0
T6 0 6 0 0
T10 2557 0 0 0
T11 0 15 0 1
T12 0 4 0 1
T17 2935 8 0 1
T23 980 0 0 0
T24 1187 0 0 0
T25 914 3 0 1
T26 0 3 0 1
T64 0 11 0 1
T77 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 3149 0 130
T5 2236 1 0 0
T6 20548 0 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T12 0 4 0 0
T13 0 22 0 1
T14 0 0 0 1
T17 2935 0 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T28 631 0 0 0
T33 1483 1 0 0
T42 0 3 0 1
T43 0 28 0 1
T44 0 1 0 0
T49 0 0 0 1
T71 0 1 0 0
T78 0 4 0 0
T79 0 3 0 1
T80 0 0 0 1
T81 0 0 0 1
T82 0 0 0 1
T83 0 0 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 2793 0 124
T6 20548 0 0 0
T10 2557 4 0 0
T11 3833 0 0 0
T12 2824 0 0 0
T13 0 3 0 1
T17 2935 0 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T28 631 0 0 0
T33 1483 0 0 0
T43 0 11 0 1
T45 0 4 0 0
T46 0 4 0 1
T47 0 1 0 0
T48 0 15 0 1
T49 0 0 0 1
T50 0 3 0 1
T53 0 4 0 0
T84 0 3 0 1
T85 0 0 0 1
T86 0 0 0 1
T87 0 0 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 3484 0 100
T4 552 0 0 0
T5 2236 0 0 0
T6 20548 0 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T13 0 27 0 1
T14 0 0 0 1
T17 2935 0 0 0
T20 0 1 0 0
T23 980 3 0 1
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T43 0 7 0 1
T51 0 4 0 0
T52 0 4 0 0
T53 0 1 0 0
T54 0 0 0 1
T60 0 3 0 1
T88 0 1 0 0
T89 0 3 0 1
T90 0 0 0 1
T91 0 0 0 1
T92 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 2764 0 89
T7 2551 1 0 0
T12 2824 0 0 0
T13 0 3 0 1
T16 23702 0 0 0
T20 2259 0 0 0
T27 995 0 0 0
T28 631 3 0 1
T29 0 3 0 1
T43 0 3 0 1
T49 0 19 0 1
T55 0 3 0 1
T56 0 1 0 0
T64 12355 0 0 0
T75 1232 0 0 0
T77 1045 0 0 0
T88 0 4 0 0
T93 0 1 0 0
T94 1360 0 0 0
T95 0 0 0 1
T96 0 0 0 1
T97 0 0 0 1
T98 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 4477 0 83
T13 0 58 0 1
T21 2325 4 0 0
T22 8195 0 0 0
T31 856 0 0 0
T43 0 31 0 1
T46 2223 0 0 0
T54 0 33 0 1
T55 1421 0 0 0
T58 0 3 0 1
T65 1276 0 0 0
T96 0 0 0 1
T98 0 0 0 1
T99 0 4 0 0
T100 0 1 0 0
T101 0 3 0 1
T102 0 1 0 0
T103 0 4 0 0
T104 1540 0 0 0
T105 2624 0 0 0
T106 14794 0 0 0
T107 1019 0 0 0
T108 0 0 0 1
T109 0 0 0 1
T110 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 538088 0 296
T1 1123 19 0 0
T2 1591 20 0 0
T3 2549 17 0 0
T4 552 160 0 0
T5 2236 1054 0 0
T6 0 0 0 2
T10 2557 1222 0 2
T16 0 0 0 2
T17 2935 622 0 0
T18 0 0 0 2
T20 0 0 0 2
T23 980 52 0 0
T24 1187 1118 0 2
T25 914 18 0 0
T41 0 0 0 2
T72 0 0 0 2
T75 0 0 0 2
T76 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 2014 0 73
T8 1811 0 0 0
T13 0 3 0 1
T14 0 0 0 1
T16 23702 0 0 0
T20 2259 4 0 0
T29 677 0 0 0
T30 1928 0 0 0
T41 2028 4 0 0
T43 0 3 0 1
T45 0 4 0 1
T59 0 3 0 1
T60 0 19 0 1
T63 0 3 0 1
T66 10776 0 0 0
T71 2164 0 0 0
T72 1024 0 0 0
T94 1360 0 0 0
T111 0 4 0 1
T112 0 1 0 0
T113 0 0 0 1
T114 0 0 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 154865 0 0
T4 552 248 0 0
T5 2236 1153 0 0
T6 20548 0 0 0
T7 0 1120 0 0
T8 0 628 0 0
T9 0 1098 0 0
T10 2557 0 0 0
T11 3833 0 0 0
T16 0 8993 0 0
T17 2935 0 0 0
T18 0 9631 0 0
T24 1187 0 0 0
T25 914 0 0 0
T26 1783 0 0 0
T32 0 29 0 0
T33 1483 620 0 0
T71 0 1102 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%