Unified Coverage Report :: Module :: edn_cov_if

Module : edn_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.00	50.00	0.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_cov_if	25.00	50.00	0.00

---

Module Instance : tb.dut.u_edn_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.00	50.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.00	50.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_cov_if

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	1	100.00

24                        bit en_intg_cov_loc;
25         0/1     ==>    assign en_intg_cov_loc = en_full_cov | en_intg_cov;
26                      
27         1/1            assign ep_requests = {ep_req[6], ep_req[5], ep_req[4], ep_req[3],
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : edn_cov_if

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (en_full_cov | en_intg_cov)
             -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered