Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.13	99.92	92.75	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T12,T25

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T19
1	0	Covered	T4,T6,T27

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T4,T10	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T23,T6	Yes	T4,T23,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T3,T4,T10	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T26,T16,T18	Yes	T26,T16,T18	INPUT
edn_i[2].edn_req	Yes	Yes	T26,T16,T37	Yes	T26,T16,T37	INPUT
edn_i[3].edn_req	Yes	Yes	T4,T10,T16	Yes	T4,T10,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T16,T38	Yes	T10,T16,T38	INPUT
edn_i[5].edn_req	Yes	Yes	T23,T16,T39	Yes	T23,T16,T39	INPUT
edn_i[6].edn_req	Yes	Yes	T16,T38,T17	Yes	T16,T38,T17	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T5,T40,T41	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T42,T25	Yes	T26,T18,T42	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T43,T44	Yes	T26,T18,T43	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T18,T42	Yes	T26,T18,T42	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T26,T37,T43	Yes	T26,T37,T43	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T26,T43,T45	Yes	T26,T43,T20	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T26,T37,T43	Yes	T26,T37,T43	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T43,T46	Yes	T10,T43,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T47,T48	Yes	T10,T43,T46	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T4,T10,T43	Yes	T4,T10,T43	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T10,T43,T45	Yes	T10,T38,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T49,T50,T51	Yes	T10,T43,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T38,T43	Yes	T10,T38,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T39,T7,T43	Yes	T23,T39,T7	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T45,T52,T13	Yes	T23,T39,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T39,T7	Yes	T23,T39,T7	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T38,T43,T20	Yes	T38,T43,T20	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T20,T53	Yes	T43,T20,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T38,T43,T54	Yes	T38,T43,T54	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T10	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T5,T26,T40	Yes	T5,T26,T40	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T5,T26,T40	Yes	T5,T11,T26	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T55,T56,T53	Yes	T55,T56,T53	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T57,T12	Yes	T10,T57,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T57,T12	Yes	T10,T57,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T40,T41	Yes	T5,T40,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	10451867	10277971	0	0
CsrngAppIfOut_A	10451867	10277971	0	0
FpvSecCmCntAlertCheck_A	10451867	121	0	0
FpvSecCmGenCmdFifoRptrCheck_A	10451867	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	10451867	70	0	0
FpvSecCmMainFsmCheck_A	10451867	70	0	0
FpvSecCmRegWeOnehotCheck_A	10451867	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	10451867	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	10451867	70	0	0
IntrEdnCmdReqDoneKnownO_A	10451867	10277971	0	0
TlAReadyKnownO_A	10451867	10277971	0	0
TlDValidKnownO_A	10451867	10277971	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	10451867	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[0].EdnDataStable_A	10451867	20766	0	428
gen_edn_if_asserts[0].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[1].EdnDataStable_A	10451867	7067	0	134
gen_edn_if_asserts[1].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[2].EdnDataStable_A	10451867	4334	0	117
gen_edn_if_asserts[2].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[3].EdnDataStable_A	10451867	3616	0	103
gen_edn_if_asserts[3].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[4].EdnDataStable_A	10451867	2010	0	110
gen_edn_if_asserts[4].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[5].EdnDataStable_A	10451867	4398	0	95
gen_edn_if_asserts[5].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	10451867	152822	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	10451867	521808	0	284
gen_edn_if_asserts[6].EdnDataStable_A	10451867	1866	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	10451867	10277971	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	10451867	152822	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	121	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T44	0	1	0	0
T58	0	20	0	0
T59	0	10	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	70	0	0
T12	3190	0	0	0
T16	27648	10	0	0
T17	0	20	0	0
T18	4156	0	0	0
T19	0	10	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T58	0	20	0	0
T59	0	10	0	0
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T65	1579	0	0	0
T66	4886	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	20766	0	428
T1	1219	3	0	1
T2	1448	3	0	1
T3	1982	3	0	1
T4	671	0	0	0
T5	10755	17	0	1
T6	1784	0	0	0
T10	2388	0	0	0
T11	1402	4	0	0
T12	0	8	0	1
T23	1118	0	0	0
T24	998	3	0	1
T26	0	3	0	1
T27	0	1	0	0
T40	0	0	0	1
T63	0	0	0	1
T69	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	7067	0	134
T12	3190	0	0	0
T13	0	3	0	1
T16	27648	0	0	0
T18	4156	4	0	0
T25	0	4	0	1
T26	1867	39	0	1
T27	780	0	0	0
T37	1219	0	0	0
T40	14978	0	0	0
T42	0	1	0	0
T43	0	59	0	1
T44	0	1	0	0
T45	0	25	0	1
T49	0	0	0	1
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T70	0	3	0	1
T71	0	62	0	1
T72	0	0	0	1
T73	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	4334	0	117
T12	3190	0	0	0
T13	0	0	0	1
T16	27648	0	0	0
T18	4156	0	0	0
T20	0	4	0	0
T26	1867	62	0	1
T27	780	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T37	1219	4	0	0
T40	14978	0	0	0
T43	0	855	0	1
T45	0	699	0	1
T49	0	0	0	1
T62	1940	0	0	0
T63	2030	0	0	0
T64	1773	0	0	0
T71	0	54	0	1
T73	0	0	0	1
T74	0	3	0	1
T75	0	4	0	0
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	3616	0	103
T4	671	1	0	0
T5	10755	0	0	0
T6	1784	0	0	0
T10	2388	4	0	0
T11	1402	0	0	0
T13	0	3	0	1
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T43	0	3	0	1
T46	0	4	0	1
T47	0	10	0	1
T48	0	1	0	0
T49	0	21	0	1
T57	1439	0	0	0
T69	1237	0	0	0
T73	0	0	0	1
T75	0	1	0	0
T78	0	3	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	2010	0	110
T5	10755	0	0	0
T6	1784	0	0	0
T10	2388	4	0	1
T11	1402	0	0	0
T13	0	3	0	1
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	780	0	0	0
T38	0	1	0	0
T43	0	3	0	1
T45	0	3	0	1
T49	0	46	0	1
T53	0	4	0	1
T57	1439	0	0	0
T69	1237	0	0	0
T71	0	3	0	1
T73	0	0	0	1
T82	0	1	0	0
T83	0	3	0	1
T84	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	4398	0	95
T5	10755	0	0	0
T6	1784	0	0	0
T7	0	1	0	0
T11	1402	0	0	0
T13	0	53	0	1
T16	27648	0	0	0
T21	0	4	0	0
T22	0	4	0	0
T23	1118	3	0	1
T24	998	0	0	0
T26	1867	0	0	0
T27	780	0	0	0
T39	0	3	0	1
T43	0	3	0	1
T45	0	42	0	1
T49	0	0	0	1
T52	0	4	0	0
T55	0	4	0	1
T57	1439	0	0	0
T69	1237	0	0	0
T73	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	521808	0	284
T1	1219	12	0	0
T2	1448	28	0	0
T3	1982	11	0	0
T4	671	142	0	0
T5	10755	879	0	0
T6	1784	356	0	0
T10	2388	186	0	0
T11	1402	403	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T20	0	0	0	2
T23	1118	33	0	0
T24	998	21	0	0
T38	0	0	0	2
T57	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	1866	0	79
T7	2436	0	0	0
T8	871	0	0	0
T13	0	3	0	1
T14	0	0	0	1
T17	52460	0	0	0
T20	0	4	0	0
T38	1735	4	0	0
T41	16012	0	0	0
T43	7362	12	0	1
T44	1358	0	0	0
T47	0	3	0	1
T49	0	3	0	1
T53	0	4	0	0
T54	0	3	0	1
T67	984	0	0	0
T73	0	0	0	1
T87	0	4	0	0
T88	0	4	0	0
T89	1554	0	0	0
T90	1573	0	0	0
T91	0	0	0	1
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	10277971	0	0
T1	1219	1143	0	0
T2	1448	1382	0	0
T3	1982	1905	0	0
T4	671	512	0	0
T5	10755	10417	0	0
T6	1784	1652	0	0
T10	2388	2336	0	0
T11	1402	1332	0	0
T23	1118	1042	0	0
T24	998	919	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10451867	152822	0	0
T4	671	224	0	0
T5	10755	0	0	0
T6	1784	401	0	0
T7	0	1092	0	0
T8	0	364	0	0
T10	2388	0	0	0
T11	1402	0	0	0
T16	0	9645	0	0
T17	0	19535	0	0
T23	1118	0	0	0
T24	998	0	0	0
T26	1867	0	0	0
T27	0	340	0	0
T42	0	263	0	0
T44	0	638	0	0
T57	1439	0	0	0
T62	0	456	0	0
T69	1237	0	0	0