Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10941589	379304	0	0
boot_gen_cmd_rd_A	10941589	2509	0	0
boot_ins_cmd_rd_A	10941589	2936	0	0
ctrl_rd_A	10941589	2658	0	0
err_code_test_rd_A	10941589	2771	0	0
intr_enable_rd_A	10941589	5916	0	0
max_num_reqs_between_reseeds_rd_A	10941589	3418	0	0
regwen_rd_A	10941589	3879	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	379304	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	3867	0	0
T35	0	9343	0	0
T36	0	13548	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T204	0	14161	0	0
T205	0	1174	0	0
T206	0	24408	0	0
T224	0	20481	0	0
T225	0	16283	0	0
T226	0	11349	0	0
T227	0	7864	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	2509	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	137	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	230	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	76	0	0
T232	0	115	0	0
T233	0	295	0	0
T234	0	399	0	0
T235	0	183	0	0
T236	0	436	0	0
T237	0	254	0	0
T238	0	100	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	2936	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	114	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	245	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	47	0	0
T232	0	143	0	0
T233	0	374	0	0
T234	0	444	0	0
T235	0	198	0	0
T236	0	683	0	0
T237	0	267	0	0
T238	0	87	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	2658	0	0
T7	2436	0	0	0
T17	52460	0	0	0
T34	0	137	0	0
T38	1735	0	0	0
T39	965	1	0	0
T41	16012	0	0	0
T43	7362	0	0	0
T44	1358	0	0	0
T46	0	3	0	0
T67	984	0	0	0
T89	1554	0	0	0
T90	1573	1	0	0
T111	0	10	0	0
T208	0	4	0	0
T239	0	2	0	0
T240	0	3	0	0
T241	0	3	0	0
T242	0	12	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	2771	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	200	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	250	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	56	0	0
T232	0	227	0	0
T233	0	288	0	0
T234	0	451	0	0
T235	0	204	0	0
T236	0	554	0	0
T237	0	192	0	0
T238	0	96	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	5916	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	287	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	470	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	108	0	0
T241	0	8	0	0
T243	0	111	0	0
T244	0	29	0	0
T245	0	9	0	0
T246	0	8	0	0
T247	0	38	0	0
T248	0	32	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	3418	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	76	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	206	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	88	0	0
T232	0	84	0	0
T233	0	244	0	0
T234	0	377	0	0
T235	0	181	0	0
T236	0	514	0	0
T237	0	207	0	0
T249	0	24	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10941589	3879	0	0
T9	1120	0	0	0
T31	731	0	0	0
T34	119439	143	0	0
T45	7903	0	0	0
T52	710	0	0	0
T56	1797	0	0	0
T58	47938	0	0	0
T226	0	330	0	0
T228	1523	0	0	0
T229	1303	0	0	0
T230	1322	0	0	0
T231	0	45	0	0
T232	0	162	0	0
T233	0	296	0	0
T234	0	461	0	0
T235	0	199	0	0
T236	0	554	0	0
T237	0	229	0	0
T249	0	28	0	0