Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.27	98.25	93.79	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.18	99.92	92.49	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T15,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T4,T5,T28

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T11,T27,T28	Yes	T11,T27,T28	INPUT
edn_i[2].edn_req	Yes	Yes	T11,T16,T17	Yes	T11,T16,T17	INPUT
edn_i[3].edn_req	Yes	Yes	T21,T11,T16	Yes	T21,T11,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T16,T20,T38	Yes	T16,T20,T38	INPUT
edn_i[5].edn_req	Yes	Yes	T16,T25,T17	Yes	T16,T25,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T4,T5	Yes	T9,T4,T5	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T39,T40,T41	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T11,T27,T28	Yes	T11,T27,T28	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T11,T28,T42	Yes	T11,T27,T28	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T11,T27,T28	Yes	T11,T27,T28	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T11,T43,T44	Yes	T11,T45,T43	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T46,T47,T48	Yes	T43,T44,T46	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T11,T45,T43	Yes	T11,T45,T43	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T11,T19,T49	Yes	T21,T11,T19	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T21,T49,T50	Yes	T21,T49,T50	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T21,T11,T19	Yes	T21,T11,T19	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T20,T38,T51	Yes	T20,T38,T51	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T52,T50,T53	Yes	T38,T51,T52	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T20,T38,T51	Yes	T20,T38,T51	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T25,T54,T55	Yes	T25,T54,T55	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T55,T56,T57	Yes	T55,T56,T58	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T54,T55	Yes	T25,T54,T55	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T20,T59	Yes	T9,T4,T20	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T4,T20,T59	Yes	T4,T20,T59	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T4,T20	Yes	T9,T4,T20	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T9,T4,T21	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T11,T27,T19	Yes	T11,T20,T41	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T21,T11,T20	Yes	T9,T11,T27	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T26,T53,T60	Yes	T26,T53,T60	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T22,T15	Yes	T10,T22,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T22	Yes	T4,T5,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T22,T15	Yes	T10,T22,T15	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T22	Yes	T4,T5,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T39,T41	Yes	T3,T39,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T28	Yes	T3,T4,T28	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	11631293	11443645	0	0
CsrngAppIfOut_A	11631293	11443645	0	0
FpvSecCmCntAlertCheck_A	11631293	127	0	0
FpvSecCmGenCmdFifoRptrCheck_A	11631293	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	11631293	80	0	0
FpvSecCmMainFsmCheck_A	11631293	80	0	0
FpvSecCmRegWeOnehotCheck_A	11631293	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	11631293	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	11631293	80	0	0
IntrEdnCmdReqDoneKnownO_A	11631293	11443645	0	0
TlAReadyKnownO_A	11631293	11443645	0	0
TlDValidKnownO_A	11631293	11443645	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	11631293	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[0].EdnDataStable_A	11631293	24401	0	418
gen_edn_if_asserts[0].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[1].EdnDataStable_A	11631293	7465	0	138
gen_edn_if_asserts[1].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[2].EdnDataStable_A	11631293	3368	0	104
gen_edn_if_asserts[2].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[3].EdnDataStable_A	11631293	4003	0	98
gen_edn_if_asserts[3].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[4].EdnDataStable_A	11631293	3742	0	82
gen_edn_if_asserts[4].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[5].EdnDataStable_A	11631293	2150	0	80
gen_edn_if_asserts[5].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	11631293	156228	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	11631293	564474	0	290
gen_edn_if_asserts[6].EdnDataStable_A	11631293	3087	0	76
gen_edn_if_asserts[6].EdnEndPointOut_A	11631293	11443645	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	11631293	156228	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	127	0	0
T6	2859	1	0	0
T7	0	1	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	1	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	80	0	0
T6	2859	0	0	0
T15	3122	0	0	0
T16	25905	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	1689	0	0	0
T20	3651	0	0	0
T24	1072	0	0	0
T39	9590	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T66	1750	0	0	0
T67	1412	0	0	0
T68	1504	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	24401	0	418
T1	1060	3	0	1
T2	836	3	0	1
T3	2121	3	0	1
T4	2163	0	0	0
T5	1415	0	0	0
T9	1129	0	0	0
T10	2622	4	0	1
T11	6508	0	0	0
T15	0	4	0	1
T21	752	0	0	0
T22	1017	0	0	0
T23	0	3	0	1
T24	0	3	0	1
T27	0	3	0	1
T66	0	3	0	1
T70	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	7465	0	138
T6	2859	0	0	0
T11	6508	1146	0	1
T12	0	15	0	1
T15	3122	0	0	0
T16	25905	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	3	0	1
T28	994	1	0	0
T42	0	1	0	0
T49	0	4	0	1
T53	0	4	0	1
T54	0	39	0	1
T56	0	0	0	1
T70	1591	0	0	0
T73	0	4	0	0
T74	0	3	0	1
T75	0	0	0	1
T76	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	3368	0	104
T6	2859	0	0	0
T11	6508	3	0	1
T12	0	23	0	1
T13	0	0	0	1
T15	3122	0	0	0
T16	25905	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	0	0	0
T43	0	3	0	1
T44	0	3	0	1
T45	0	4	0	0
T46	0	1	0	0
T47	0	4	0	0
T48	0	4	0	0
T56	0	0	0	1
T57	0	0	0	1
T70	1591	0	0	0
T77	0	1	0	0
T78	0	4	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	4003	0	98
T5	1415	0	0	0
T10	2622	0	0	0
T11	6508	3	0	1
T16	25905	0	0	0
T19	0	4	0	0
T21	752	3	0	1
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	0	0	0
T44	0	3	0	1
T49	0	927	0	1
T50	0	20	0	1
T54	0	0	0	1
T61	0	1	0	0
T70	1591	0	0	0
T77	0	4	0	0
T81	0	4	0	0
T82	0	3	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	3742	0	82
T7	1112	0	0	0
T20	3651	3	0	1
T25	847	0	0	0
T26	2786	0	0	0
T38	2638	4	0	0
T40	2111	0	0	0
T41	9192	0	0	0
T44	0	3	0	1
T50	0	26	0	1
T51	0	3	0	1
T52	0	4	0	0
T54	0	0	0	1
T56	0	0	0	1
T59	0	4	0	0
T69	1818	0	0	0
T71	0	1	0	0
T86	0	4	0	1
T87	0	4	0	0
T88	1780	0	0	0
T89	1951	0	0	0
T90	0	0	0	1
T91	0	0	0	1
T92	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	2150	0	80
T14	0	0	0	1
T17	26363	0	0	0
T25	847	3	0	1
T38	2638	0	0	0
T41	9192	0	0	0
T49	7006	0	0	0
T51	1305	0	0	0
T54	0	3	0	1
T55	0	1	0	0
T56	0	43	0	1
T57	0	4	0	0
T58	0	4	0	1
T71	932	0	0	0
T72	1876	0	0	0
T88	1780	0	0	0
T89	1951	0	0	0
T93	0	1	0	0
T94	0	4	0	0
T95	0	4	0	0
T96	0	3	0	1
T97	0	0	0	1
T98	0	0	0	1
T99	0	0	0	1
T100	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	564474	0	290
T1	1060	19	0	0
T2	836	17	0	0
T3	2121	22	0	0
T4	2163	1072	0	0
T5	1415	222	0	0
T9	1129	198	0	2
T10	2622	706	0	0
T11	6508	71	0	0
T16	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T21	752	56	0	0
T22	1017	940	0	2
T38	0	0	0	2
T39	0	0	0	2
T45	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	3087	0	76
T4	2163	1	0	0
T5	1415	0	0	0
T9	1129	4	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T14	0	0	0	1
T20	0	180	0	1
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T54	0	3	0	1
T59	0	4	0	0
T70	1591	0	0	0
T98	0	0	0	1
T101	0	1	0	0
T102	0	4	0	0
T103	0	3	0	1
T104	0	4	0	0
T105	0	4	0	1
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	156228	0	0
T4	2163	30	0	0
T5	1415	657	0	0
T6	0	652	0	0
T7	0	273	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	0	11622	0	0
T17	0	7765	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	397	0	0
T40	0	1110	0	0
T70	1591	0	0	0
T71	0	402	0	0
T72	0	1144	0	0