Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12107741	452647	0	0
boot_gen_cmd_rd_A	12107741	1719	0	0
boot_ins_cmd_rd_A	12107741	1859	0	0
ctrl_rd_A	12107741	1820	0	0
err_code_test_rd_A	12107741	1848	0	0
intr_enable_rd_A	12107741	4611	0	0
max_num_reqs_between_reseeds_rd_A	12107741	2198	0	0
regwen_rd_A	12107741	2426	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	452647	0	0
T35	177210	11217	0	0
T36	0	5882	0	0
T37	0	8141	0	0
T76	5096	0	0	0
T95	1128	0	0	0
T102	2370	0	0	0
T139	2190	0	0	0
T211	2774	0	0	0
T243	0	6758	0	0
T244	0	13388	0	0
T245	0	16175	0	0
T246	0	6476	0	0
T247	0	9124	0	0
T248	0	21090	0	0
T249	0	8050	0	0
T250	988	0	0	0
T251	1000	0	0	0
T252	1342	0	0	0
T253	2125	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	1719	0	0
T36	161448	79	0	0
T37	237601	215	0	0
T161	3992	0	0	0
T243	106837	0	0	0
T254	0	343	0	0
T255	0	311	0	0
T256	0	77	0	0
T257	0	174	0	0
T258	0	250	0	0
T259	0	5	0	0
T260	0	94	0	0
T261	0	4	0	0
T262	3948	0	0	0
T263	1138	0	0	0
T264	2179	0	0	0
T265	11255	0	0	0
T266	1974	0	0	0
T267	21686	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	1859	0	0
T36	161448	115	0	0
T37	237601	306	0	0
T161	3992	0	0	0
T243	106837	0	0	0
T254	0	294	0	0
T255	0	261	0	0
T256	0	66	0	0
T257	0	212	0	0
T258	0	291	0	0
T259	0	7	0	0
T260	0	102	0	0
T262	3948	0	0	0
T263	1138	0	0	0
T264	2179	0	0	0
T265	11255	0	0	0
T266	1974	0	0	0
T267	21686	0	0	0
T268	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	1820	0	0
T5	1415	9	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	0	0	0
T32	0	9	0	0
T36	0	69	0	0
T37	0	226	0	0
T68	0	7	0	0
T70	1591	0	0	0
T181	0	8	0	0
T239	0	7	0	0
T254	0	200	0	0
T269	0	7	0	0
T270	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	1848	0	0
T36	161448	133	0	0
T37	237601	351	0	0
T161	3992	0	0	0
T243	106837	0	0	0
T254	0	278	0	0
T255	0	313	0	0
T256	0	61	0	0
T257	0	246	0	0
T258	0	230	0	0
T259	0	3	0	0
T260	0	80	0	0
T261	0	3	0	0
T262	3948	0	0	0
T263	1138	0	0	0
T264	2179	0	0	0
T265	11255	0	0	0
T266	1974	0	0	0
T267	21686	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	4611	0	0
T7	1112	0	0	0
T20	3651	0	0	0
T25	847	0	0	0
T26	2786	0	0	0
T36	0	241	0	0
T37	0	727	0	0
T38	2638	0	0	0
T39	9590	31	0	0
T40	2111	0	0	0
T41	9192	0	0	0
T68	1504	0	0	0
T69	1818	0	0	0
T119	0	67	0	0
T122	0	28	0	0
T254	0	495	0	0
T267	0	80	0	0
T270	0	10	0	0
T271	0	104	0	0
T272	0	49	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	2198	0	0
T36	161448	91	0	0
T37	237601	173	0	0
T161	3992	0	0	0
T243	106837	0	0	0
T254	0	215	0	0
T255	0	311	0	0
T256	0	105	0	0
T257	0	285	0	0
T258	0	193	0	0
T259	0	4	0	0
T260	0	114	0	0
T262	3948	0	0	0
T263	1138	0	0	0
T264	2179	0	0	0
T265	11255	0	0	0
T266	1974	0	0	0
T267	21686	0	0	0
T268	0	9	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12107741	2426	0	0
T36	161448	116	0	0
T37	237601	310	0	0
T161	3992	0	0	0
T243	106837	0	0	0
T254	0	317	0	0
T255	0	358	0	0
T256	0	85	0	0
T257	0	222	0	0
T258	0	279	0	0
T259	0	1	0	0
T260	0	130	0	0
T262	3948	0	0	0
T263	1138	0	0	0
T264	2179	0	0	0
T265	11255	0	0	0
T266	1974	0	0	0
T267	21686	0	0	0
T268	0	3	0	0