Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.07	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.18	99.92	92.75	82.84	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T18,T11,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T20,T21
1	0	Covered	T4,T5,T19

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T18,T10,T31	Yes	T18,T10,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T18,T16,T11	Yes	T18,T16,T11	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T18,T40	Yes	T3,T18,T40	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T10,T17	Yes	T3,T10,T17	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T28,T40	Yes	T3,T28,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T40,T17	Yes	T3,T40,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T5,T17	Yes	T3,T5,T17	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T30,T6	Yes	T1,T2,T30	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T6,T40	Yes	T2,T4,T30	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T18,T11,T41	Yes	T18,T11,T41	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T41,T42,T43	Yes	T41,T22,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T18,T11,T41	Yes	T18,T11,T41	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T18,T40	Yes	T3,T18,T40	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T3,T40,T44	Yes	T3,T40,T15	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T18,T40	Yes	T3,T18,T40	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T45,T46	Yes	T3,T10,T45	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T47,T48,T49	Yes	T45,T46,T47	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T10,T45	Yes	T3,T10,T45	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T28,T40	Yes	T3,T28,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T50,T51	Yes	T3,T40,T15	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T28,T40	Yes	T3,T28,T40	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T40,T52,T42	Yes	T3,T40,T53	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T54,T55,T51	Yes	T52,T23,T54	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T40,T53	Yes	T3,T40,T53	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T56,T57,T25	Yes	T3,T56,T57	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T57,T34,T54	Yes	T57,T34,T25	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T56,T57	Yes	T3,T56,T57	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T18	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T40,T53	Yes	T3,T6,T40	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T10,T6	Yes	T3,T10,T6	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T11,T58,T59	Yes	T11,T58,T59	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T29,T11	Yes	T18,T29,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T29,T5	Yes	T4,T29,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T29,T11	Yes	T18,T29,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T29,T5	Yes	T4,T29,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T60,T61	Yes	T6,T60,T61	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	10609786	10420700	0	0
CsrngAppIfOut_A	10609786	10420700	0	0
FpvSecCmCntAlertCheck_A	10609786	114	0	0
FpvSecCmGenCmdFifoRptrCheck_A	10609786	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	10609786	80	0	0
FpvSecCmMainFsmCheck_A	10609786	80	0	0
FpvSecCmRegWeOnehotCheck_A	10609786	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	10609786	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	10609786	80	0	0
IntrEdnCmdReqDoneKnownO_A	10609786	10420700	0	0
TlAReadyKnownO_A	10609786	10420700	0	0
TlDValidKnownO_A	10609786	10420700	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	10609786	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[0].EdnDataStable_A	10609786	120755	0	404
gen_edn_if_asserts[0].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[1].EdnDataStable_A	10609786	55980	0	125
gen_edn_if_asserts[1].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[2].EdnDataStable_A	10609786	3988	0	116
gen_edn_if_asserts[2].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[3].EdnDataStable_A	10609786	4688	0	102
gen_edn_if_asserts[3].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[4].EdnDataStable_A	10609786	6845	0	107
gen_edn_if_asserts[4].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[5].EdnDataStable_A	10609786	2294	0	98
gen_edn_if_asserts[5].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	10609786	158573	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	10609786	537853	0	282
gen_edn_if_asserts[6].EdnDataStable_A	10609786	2750	0	72
gen_edn_if_asserts[6].EdnEndPointOut_A	10609786	10420700	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	10609786	158573	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	114	0	0
T7	1824	1	0	0
T11	2540	0	0	0
T15	2822	0	0	0
T16	1863	1	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T56	928	0	0	0
T58	0	1	0	0
T60	6078	0	0	0
T62	0	10	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	80	0	0
T15	2822	0	0	0
T17	27531	10	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	20	0	0
T33	1999	0	0	0
T41	3893	0	0	0
T56	928	0	0	0
T60	6078	0	0	0
T62	0	10	0	0
T65	1502	0	0	0
T66	1088	0	0	0
T67	2162	0	0	0
T68	865	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	120755	0	404
T1	1410	3	0	1
T2	1470	3	0	1
T3	2462	0	0	0
T4	1132	1	0	0
T5	2395	0	0	0
T6	0	10	0	0
T10	3107	0	0	0
T11	0	4	0	1
T18	2023	0	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	3	0	1
T31	0	3	0	1
T40	0	54	0	1
T60	0	3	0	1
T65	0	3	0	1
T66	0	0	0	1
T70	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	55980	0	125
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T11	0	4	0	0
T18	2023	4	0	0
T19	2322	0	0	0
T22	0	4	0	0
T24	0	4	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T41	0	18	0	1
T42	0	23	0	1
T43	0	48	0	1
T46	0	4	0	0
T53	0	4	0	0
T54	0	0	0	1
T72	0	529	0	1
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	3988	0	116
T3	2462	40	0	1
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T15	0	4	0	0
T18	2023	4	0	1
T19	0	1	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T32	0	4	0	1
T40	0	33	0	1
T43	0	3	0	1
T44	0	4	0	0
T45	0	15	0	1
T54	0	0	0	1
T59	0	4	0	1
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	4688	0	102
T3	2462	3	0	1
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	4	0	0
T18	2023	0	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T45	0	4	0	1
T46	0	4	0	1
T47	0	1	0	0
T48	0	0	0	1
T49	0	0	0	1
T54	0	4	0	1
T76	0	0	0	1
T80	0	3	0	1
T81	0	4	0	0
T82	0	4	0	0
T83	0	4	0	0
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	6845	0	107
T3	2462	53	0	1
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T15	0	1	0	0
T18	2023	0	0	0
T27	0	4	0	0
T28	719	3	0	1
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	0	3	0	1
T50	0	8	0	1
T51	0	0	0	1
T68	0	3	0	1
T86	0	3	0	1
T87	0	3	0	1
T88	0	4	0	1
T89	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	2294	0	98
T3	2462	3	0	1
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T18	2023	0	0	0
T23	0	1	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	0	3	0	1
T42	0	3	0	1
T51	0	0	0	1
T52	0	3	0	1
T53	0	1	0	0
T54	0	32	0	1
T83	0	0	0	1
T90	0	4	0	1
T91	0	3	0	1
T92	0	4	0	0
T93	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	537853	0	282
T1	1410	23	0	0
T2	1470	16	0	0
T3	2462	11	0	0
T4	1132	530	0	0
T5	2395	85	0	0
T10	3107	1130	0	2
T15	0	0	0	2
T17	0	0	0	2
T18	2023	435	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T28	719	76	0	0
T29	1623	1534	0	2
T30	1816	28	0	0
T53	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	2750	0	72
T3	2462	3	0	1
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T13	0	0	0	1
T18	2023	0	0	0
T25	0	4	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T34	0	1	0	0
T49	0	0	0	1
T54	0	24	0	1
T56	0	3	0	1
T57	0	63	0	1
T76	0	0	0	1
T94	0	4	0	0
T95	0	4	0	0
T96	0	4	0	0
T97	0	4	0	0
T98	0	0	0	1
T99	0	0	0	1
T100	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	158573	0	0
T4	1132	7	0	0
T5	2395	726	0	0
T6	15376	0	0	0
T7	0	855	0	0
T8	0	1082	0	0
T10	3107	0	0	0
T16	0	1104	0	0
T17	0	11008	0	0
T18	2023	0	0	0
T19	0	24	0	0
T20	0	22113	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T33	0	7	0	0
T40	3356	0	0	0
T71	0	1070	0	0