Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11205008	334266	0	0
boot_gen_cmd_rd_A	11205008	3550	0	0
boot_ins_cmd_rd_A	11205008	4190	0	0
ctrl_rd_A	11205008	3711	0	0
err_code_test_rd_A	11205008	3858	0	0
intr_enable_rd_A	11205008	9374	0	0
max_num_reqs_between_reseeds_rd_A	11205008	5550	0	0
regwen_rd_A	11205008	6067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	334266	0	0
T27	3746	0	0	0
T37	179331	6344	0	0
T38	0	7454	0	0
T39	0	4880	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T231	0	18223	0	0
T232	0	8669	0	0
T233	0	26885	0	0
T234	0	9233	0	0
T235	0	18465	0	0
T236	0	10346	0	0
T237	0	12679	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	3550	0	0
T27	3746	0	0	0
T37	179331	232	0	0
T39	0	112	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T235	0	521	0	0
T236	0	376	0	0
T237	0	215	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0
T243	0	310	0	0
T244	0	202	0	0
T245	0	261	0	0
T246	0	335	0	0
T247	0	359	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	4190	0	0
T27	3746	0	0	0
T37	179331	227	0	0
T39	0	172	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T235	0	635	0	0
T236	0	399	0	0
T237	0	198	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0
T243	0	419	0	0
T244	0	190	0	0
T245	0	335	0	0
T246	0	366	0	0
T247	0	455	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	3711	0	0
T2	1470	1	0	0
T3	2462	0	0	0
T4	1132	0	0	0
T5	2395	8	0	0
T10	3107	0	0	0
T18	2023	0	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T37	0	251	0	0
T39	0	134	0	0
T110	0	3	0	0
T112	0	7	0	0
T113	0	2	0	0
T155	0	4	0	0
T248	0	3	0	0
T249	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	3858	0	0
T27	3746	0	0	0
T37	179331	193	0	0
T39	0	157	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T235	0	514	0	0
T236	0	369	0	0
T237	0	238	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0
T243	0	268	0	0
T244	0	187	0	0
T245	0	349	0	0
T246	0	356	0	0
T247	0	427	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	9374	0	0
T21	48412	0	0	0
T22	2366	0	0	0
T34	684	0	0	0
T37	0	430	0	0
T39	0	360	0	0
T42	2003	0	0	0
T59	3136	0	0	0
T112	14052	21	0	0
T116	1550	0	0	0
T130	1044	0	0	0
T207	731	0	0	0
T210	0	16	0	0
T235	0	871	0	0
T236	0	870	0	0
T237	0	569	0	0
T250	0	68	0	0
T251	0	52	0	0
T252	0	23	0	0
T253	1284	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	5550	0	0
T27	3746	0	0	0
T37	179331	238	0	0
T39	0	118	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T235	0	575	0	0
T236	0	407	0	0
T237	0	224	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0
T243	0	332	0	0
T244	0	170	0	0
T245	0	262	0	0
T246	0	288	0	0
T247	0	423	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11205008	6067	0	0
T27	3746	0	0	0
T37	179331	293	0	0
T39	0	174	0	0
T79	748	0	0	0
T80	2311	0	0	0
T134	1475	0	0	0
T235	0	581	0	0
T236	0	368	0	0
T237	0	283	0	0
T238	1231	0	0	0
T239	1604	0	0	0
T240	1728	0	0	0
T241	1351	0	0	0
T242	1289	0	0	0
T243	0	386	0	0
T244	0	169	0	0
T245	0	317	0	0
T246	0	364	0	0
T247	0	433	0	0