Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.23	93.97	97.07	91.28	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	94.09	99.92	92.75	82.84	91.28	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T20,T26,T27

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T3,T4,T28

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T19	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T20	Yes	T1,T2,T20	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T20	Yes	T1,T2,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T28,T36	Yes	T3,T28,T36	INPUT
edn_i[2].edn_req	Yes	Yes	T36,T14,T15	Yes	T36,T14,T15	INPUT
edn_i[3].edn_req	Yes	Yes	T19,T9,T10	Yes	T19,T9,T10	INPUT
edn_i[4].edn_req	Yes	Yes	T36,T26,T15	Yes	T36,T26,T15	INPUT
edn_i[5].edn_req	Yes	Yes	T37,T15,T38	Yes	T37,T15,T38	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T36,T15	Yes	T9,T36,T15	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T20,T21	Yes	T1,T2,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T20,T21,T39	Yes	T2,T20,T21	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T20	Yes	T1,T2,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T36,T27	Yes	T3,T36,T27	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T3,T28,T27	Yes	T3,T28,T36	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T28,T36	Yes	T3,T28,T36	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T14,T40,T41	Yes	T36,T14,T40	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T14,T40,T41	Yes	T36,T14,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T36,T14,T40	Yes	T36,T14,T40	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T19,T14,T18	Yes	T19,T10,T14	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T42,T43,T44	Yes	T10,T18,T42	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T19,T9,T10	Yes	T19,T9,T10	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T36,T26,T45	Yes	T36,T26,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T36,T41,T46	Yes	T36,T26,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T36,T26,T45	Yes	T36,T26,T45	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T37,T38,T47	Yes	T37,T38,T47	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T47,T48,T49	Yes	T37,T38,T47	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T37,T38,T42	Yes	T37,T38,T42	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T36,T7	Yes	T9,T36,T7	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T7,T41,T50	Yes	T7,T41,T50	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T36,T7	Yes	T9,T36,T7	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T19,T4	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T19,T21,T36	Yes	T21,T9,T36	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T21,T9,T36	Yes	T19,T21,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T20,T26,T51	Yes	T20,T26,T51	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T22,T26	Yes	T20,T22,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T22,T26	Yes	T20,T22,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T39,T52	Yes	T5,T39,T52	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T5,T28	Yes	T3,T5,T28	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	12748067	12572079	0	0
CsrngAppIfOut_A	12748067	12572079	0	0
FpvSecCmCntAlertCheck_A	12748067	106	0	0
FpvSecCmGenCmdFifoRptrCheck_A	12748067	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	12748067	70	0	0
FpvSecCmMainFsmCheck_A	12748067	70	0	0
FpvSecCmRegWeOnehotCheck_A	12748067	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	12748067	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	12748067	70	0	0
IntrEdnCmdReqDoneKnownO_A	12748067	12572079	0	0
TlAReadyKnownO_A	12748067	12572079	0	0
TlDValidKnownO_A	12748067	12572079	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	12748067	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[0].EdnDataStable_A	12748067	73563	0	415
gen_edn_if_asserts[0].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[1].EdnDataStable_A	12748067	54462	0	116
gen_edn_if_asserts[1].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[2].EdnDataStable_A	12748067	6146	0	109
gen_edn_if_asserts[2].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[3].EdnDataStable_A	12748067	3655	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[4].EdnDataStable_A	12748067	1555	0	93
gen_edn_if_asserts[4].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[5].EdnDataStable_A	12748067	3855	0	93
gen_edn_if_asserts[5].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	12748067	149760	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	12748067	560591	0	310
gen_edn_if_asserts[6].EdnDataStable_A	12748067	2160	0	69
gen_edn_if_asserts[6].EdnEndPointOut_A	12748067	12572079	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	12748067	149760	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	106	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T43	0	1	0	0
T52	20814	0	0	0
T53	0	10	0	0
T54	0	1	0	0
T55	0	10	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	70	0	0
T7	1150	0	0	0
T15	50677	20	0	0
T16	61732	20	0	0
T17	0	10	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T29	1210	0	0	0
T38	728	0	0	0
T52	20814	0	0	0
T53	0	10	0	0
T55	0	10	0	0
T59	1068	0	0	0
T60	1452	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	73563	0	415
T1	1011	3	0	1
T2	1118	3	0	1
T3	838	0	0	0
T4	1125	0	0	0
T5	10902	3	0	0
T19	762	0	0	0
T20	1642	8	0	1
T21	2388	52	0	1
T22	905	0	0	0
T23	1632	3	0	1
T24	0	3	0	1
T25	0	0	0	1
T36	0	9	0	1
T39	0	16	0	1
T62	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	54462	0	116
T3	838	1	0	0
T4	1125	0	0	0
T5	10902	0	0	0
T9	3747	0	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T27	0	4	0	0
T28	0	1	0	0
T36	0	4	0	1
T44	0	0	0	1
T49	0	3	0	1
T64	0	4	0	0
T65	0	3	0	1
T66	0	3	0	1
T67	0	4	0	1
T68	0	1	0	0
T69	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	6146	0	109
T6	1282	0	0	0
T10	3453	0	0	0
T14	3185	237	0	1
T25	1626	0	0	0
T26	1984	0	0	0
T36	2953	3	0	1
T37	930	0	0	0
T39	14459	0	0	0
T40	0	4	0	0
T41	0	39	0	1
T44	0	0	0	1
T48	0	3	0	1
T61	982	0	0	0
T62	1493	0	0	0
T73	0	4	0	0
T74	0	3	0	1
T75	0	4	0	1
T76	0	3	0	1
T77	0	62	0	1
T78	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	3655	0	106
T4	1125	0	0	0
T5	10902	0	0	0
T9	3747	1	0	0
T10	0	4	0	0
T11	0	0	0	1
T14	0	3	0	1
T18	0	4	0	0
T19	762	4	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	1873	0	0	0
T42	0	651	0	1
T43	0	1	0	0
T44	0	0	0	1
T67	0	4	0	0
T74	0	3	0	1
T79	0	1	0	0
T80	0	0	0	1
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	1555	0	93
T6	1282	0	0	0
T10	3453	0	0	0
T14	3185	0	0	0
T25	1626	0	0	0
T26	1984	4	0	1
T36	2953	21	0	1
T37	930	0	0	0
T39	14459	0	0	0
T41	0	46	0	1
T45	0	4	0	0
T48	0	17	0	1
T61	982	0	0	0
T62	1493	0	0	0
T79	0	4	0	0
T85	0	4	0	0
T86	0	4	0	0
T87	0	4	0	1
T88	0	4	0	1
T89	0	0	0	1
T90	0	0	0	1
T91	0	0	0	1
T92	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	3855	0	93
T10	3453	0	0	0
T14	3185	0	0	0
T15	50677	0	0	0
T25	1626	0	0	0
T26	1984	0	0	0
T29	1210	0	0	0
T31	0	1	0	0
T37	930	3	0	1
T38	0	3	0	1
T39	14459	0	0	0
T42	0	3	0	1
T47	0	4	0	0
T48	0	15	0	1
T49	0	44	0	1
T51	0	4	0	1
T61	982	0	0	0
T62	1493	0	0	0
T78	0	0	0	1
T93	0	4	0	1
T94	0	4	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	560591	0	310
T1	1011	16	0	0
T2	1118	12	0	0
T3	838	297	0	0
T4	1125	545	0	0
T5	10902	2142	0	2
T9	0	0	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	762	61	0	0
T20	1642	138	0	0
T21	2388	29	0	0
T22	905	825	0	2
T23	1632	20	0	0
T59	0	0	0	2
T61	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	2160	0	69
T6	1282	0	0	0
T7	0	1	0	0
T9	3747	4	0	0
T10	3453	0	0	0
T24	1393	0	0	0
T26	1984	0	0	0
T28	1873	0	0	0
T36	2953	3	0	1
T37	930	0	0	0
T39	14459	0	0	0
T41	0	5	0	1
T46	0	0	0	1
T50	0	4	0	0
T61	982	0	0	0
T97	0	3	0	1
T98	0	1	0	0
T99	0	4	0	0
T100	0	4	0	0
T101	0	4	0	0
T102	0	0	0	1
T103	0	0	0	1
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	12572079	0	0
T1	1011	949	0	0
T2	1118	1051	0	0
T3	838	670	0	0
T4	1125	947	0	0
T5	10902	10773	0	0
T19	762	703	0	0
T20	1642	1586	0	0
T21	2388	2337	0	0
T22	905	827	0	0
T23	1632	1556	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12748067	149760	0	0
T3	838	28	0	0
T4	1125	612	0	0
T5	10902	0	0	0
T6	0	612	0	0
T7	0	253	0	0
T9	3747	0	0	0
T15	0	22839	0	0
T16	0	19903	0	0
T17	0	9967	0	0
T19	762	0	0	0
T20	1642	0	0	0
T21	2388	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T28	0	7	0	0
T29	0	15	0	0
T63	0	32	0	0