Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13208000	436200	0	0
boot_gen_cmd_rd_A	13208000	4384	0	0
boot_ins_cmd_rd_A	13208000	5029	0	0
ctrl_rd_A	13208000	4434	0	0
err_code_test_rd_A	13208000	4731	0	0
intr_enable_rd_A	13208000	8784	0	0
max_num_reqs_between_reseeds_rd_A	13208000	4714	0	0
regwen_rd_A	13208000	5194	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	436200	0	0
T31	1265	0	0	0
T33	146695	4651	0	0
T34	0	4995	0	0
T35	0	10536	0	0
T66	1239	0	0	0
T127	0	4141	0	0
T151	2561	0	0	0
T185	623	0	0	0
T212	0	14509	0	0
T233	0	17542	0	0
T234	0	15096	0	0
T235	0	5379	0	0
T236	0	7086	0	0
T237	0	8988	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	4384	0	0
T31	1265	0	0	0
T33	146695	209	0	0
T34	0	183	0	0
T35	0	371	0	0
T66	1239	0	0	0
T151	2561	0	0	0
T185	623	0	0	0
T235	0	130	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0
T243	0	427	0	0
T244	0	166	0	0
T245	0	201	0	0
T246	0	499	0	0
T247	0	107	0	0
T248	0	233	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	5029	0	0
T31	1265	0	0	0
T33	146695	219	0	0
T34	0	176	0	0
T35	0	416	0	0
T66	1239	0	0	0
T151	2561	0	0	0
T185	623	0	0	0
T235	0	205	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0
T243	0	358	0	0
T244	0	239	0	0
T245	0	196	0	0
T246	0	494	0	0
T247	0	139	0	0
T248	0	192	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	4434	0	0
T16	61732	0	0	0
T17	30321	0	0	0
T18	4380	0	0	0
T27	2490	0	0	0
T33	0	159	0	0
T34	0	199	0	0
T35	0	458	0	0
T42	5271	0	0	0
T52	20814	1	0	0
T59	1068	0	0	0
T60	1452	0	0	0
T63	874	0	0	0
T116	0	11	0	0
T126	0	8	0	0
T213	0	1	0	0
T235	0	144	0	0
T249	0	5	0	0
T250	0	1	0	0
T251	1194	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	4731	0	0
T31	1265	0	0	0
T33	146695	190	0	0
T34	0	184	0	0
T35	0	394	0	0
T66	1239	0	0	0
T151	2561	0	0	0
T185	623	0	0	0
T235	0	142	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0
T243	0	453	0	0
T244	0	167	0	0
T245	0	148	0	0
T246	0	414	0	0
T247	0	162	0	0
T248	0	217	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	8784	0	0
T5	10902	33	0	0
T6	1282	0	0	0
T9	3747	0	0	0
T22	905	0	0	0
T23	1632	0	0	0
T24	1393	0	0	0
T26	1984	0	0	0
T28	1873	0	0	0
T33	0	326	0	0
T34	0	336	0	0
T35	0	686	0	0
T36	2953	0	0	0
T37	930	0	0	0
T52	0	21	0	0
T116	0	125	0	0
T235	0	404	0	0
T239	0	36	0	0
T250	0	43	0	0
T252	0	80	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	4714	0	0
T31	1265	0	0	0
T33	146695	120	0	0
T34	0	201	0	0
T35	0	377	0	0
T66	1239	0	0	0
T151	2561	0	0	0
T185	623	0	0	0
T235	0	139	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0
T243	0	319	0	0
T244	0	166	0	0
T245	0	190	0	0
T246	0	503	0	0
T247	0	213	0	0
T248	0	215	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13208000	5194	0	0
T31	1265	0	0	0
T33	146695	234	0	0
T34	0	130	0	0
T35	0	490	0	0
T66	1239	0	0	0
T151	2561	0	0	0
T185	623	0	0	0
T235	0	140	0	0
T238	1230	0	0	0
T239	17493	0	0	0
T240	1702	0	0	0
T241	1129	0	0	0
T242	1685	0	0	0
T243	0	329	0	0
T244	0	231	0	0
T245	0	202	0	0
T246	0	449	0	0
T247	0	167	0	0
T248	0	228	0	0