Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.48	98.23	93.91	97.02	93.60	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	94.41	99.92	92.66	82.54	93.60	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T19,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T4,T5,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T9,T25	Yes	T1,T9,T25	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T9,T10,T25	Yes	T9,T10,T25	INPUT
edn_i[2].edn_req	Yes	Yes	T30,T16,T42	Yes	T30,T16,T42	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T16,T19	Yes	T3,T16,T19	INPUT
edn_i[4].edn_req	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
edn_i[5].edn_req	Yes	Yes	T30,T16,T31	Yes	T30,T16,T31	INPUT
edn_i[6].edn_req	Yes	Yes	T16,T7,T43	Yes	T16,T7,T43	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T10,T26	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T28,T14,T44	Yes	T2,T10,T26	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T9,T25,T15	Yes	T9,T10,T25	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T25,T45,T46	Yes	T25,T15,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T9,T10,T25	Yes	T9,T10,T25	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T30,T48,T49	Yes	T30,T42,T48	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T30,T49,T50	Yes	T30,T42,T49	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T30,T42,T48	Yes	T30,T42,T48	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T19,T51,T52	Yes	T3,T19,T51	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T51,T52,T53	Yes	T3,T51,T52	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T19,T51	Yes	T3,T19,T51	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T21,T54,T55	Yes	T20,T21,T54	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T54,T56,T57	Yes	T20,T54,T56	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T20,T21,T54	Yes	T20,T21,T54	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T30,T58,T59	Yes	T30,T31,T58	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T30,T60,T61	Yes	T30,T58,T62	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T30,T31,T58	Yes	T30,T31,T58	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T43,T63,T52	Yes	T43,T63,T52	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T64,T65	Yes	T43,T63,T52	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T43,T63,T52	Yes	T43,T63,T52	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T9	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T10,T30,T28	Yes	T10,T25,T30	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T10,T25,T30	Yes	T10,T30,T66	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T19,T32	Yes	T9,T19,T32	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T27,T67	Yes	T9,T27,T67	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T27,T67	Yes	T9,T27,T67	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T28,T68,T69	Yes	T28,T68,T69	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T28,T44	Yes	T4,T28,T44	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	9767389	9582372	0	0
CsrngAppIfOut_A	9767389	9582372	0	0
FpvSecCmCntAlertCheck_A	9767389	129	0	0
FpvSecCmGenCmdFifoRptrCheck_A	9767389	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	9767389	80	0	0
FpvSecCmMainFsmCheck_A	9767389	80	0	0
FpvSecCmRegWeOnehotCheck_A	9767389	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	9767389	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	9767389	80	0	0
IntrEdnCmdReqDoneKnownO_A	9767389	9582372	0	0
TlAReadyKnownO_A	9767389	9582372	0	0
TlDValidKnownO_A	9767389	9582372	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	9767389	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[0].EdnDataStable_A	9767389	21120	0	404
gen_edn_if_asserts[0].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[1].EdnDataStable_A	9767389	3582	0	128
gen_edn_if_asserts[1].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[2].EdnDataStable_A	9767389	4412	0	108
gen_edn_if_asserts[2].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[3].EdnDataStable_A	9767389	4201	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[4].EdnDataStable_A	9767389	3884	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[5].EdnDataStable_A	9767389	6463	0	89
gen_edn_if_asserts[5].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	9767389	142346	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	9767389	550199	0	276
gen_edn_if_asserts[6].EdnDataStable_A	9767389	2428	0	81
gen_edn_if_asserts[6].EdnEndPointOut_A	9767389	9582372	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	9767389	142346	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	129	0	0
T4	761	1	0	0
T5	1965	0	0	0
T6	4670	0	0	0
T7	0	1	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T22	0	20	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T51	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	10	0	0
T73	1732	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	80	0	0
T7	2081	0	0	0
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	20	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	2250	0	0	0
T22	0	20	0	0
T29	1091	0	0	0
T31	904	0	0	0
T44	2154	0	0	0
T67	1803	0	0	0
T72	0	10	0	0
T74	1195	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	21120	0	404
T1	940	3	0	1
T2	1788	3	0	1
T3	2682	0	0	0
T4	761	1	0	0
T5	1965	0	0	0
T6	0	3	0	1
T9	2116	0	0	0
T10	2083	4	0	0
T14	0	15	0	1
T25	1012	0	0	0
T26	1349	3	0	1
T27	1110	0	0	0
T28	0	19	0	1
T29	0	0	0	1
T44	0	1	0	0
T66	0	0	0	1
T73	0	3	0	1
T74	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	3582	0	128
T5	1965	0	0	0
T6	4670	0	0	0
T9	2116	4	0	1
T10	2083	1	0	0
T15	0	4	0	0
T25	1012	3	0	1
T26	1349	0	0	0
T27	1110	0	0	0
T28	20930	0	0	0
T30	2817	0	0	0
T45	0	4	0	0
T46	0	0	0	1
T47	0	3	0	1
T54	0	3	0	1
T56	0	0	0	1
T73	1732	0	0	0
T79	0	4	0	1
T80	0	4	0	0
T81	0	3	0	1
T82	0	0	0	1
T83	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	4412	0	108
T6	4670	0	0	0
T11	0	0	0	1
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	0	0	0
T28	20930	0	0	0
T29	1091	0	0	0
T30	2817	45	0	1
T36	0	1	0	0
T42	0	4	0	0
T44	2154	0	0	0
T48	0	4	0	1
T49	0	4	0	0
T50	0	4	0	0
T53	0	0	0	1
T67	1803	0	0	0
T74	1195	0	0	0
T82	0	54	0	1
T83	0	0	0	1
T84	0	8	0	1
T85	0	1	0	0
T86	0	57	0	1
T87	0	0	0	1
T88	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	4201	0	106
T3	2682	3	0	1
T4	761	0	0	0
T5	1965	0	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T19	0	4	0	1
T23	0	4	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T51	0	1	0	0
T52	0	4	0	0
T56	0	3	0	1
T73	1732	0	0	0
T83	0	0	0	1
T86	0	0	0	1
T89	0	4	0	0
T90	0	4	0	0
T91	0	4	0	1
T92	0	3	0	1
T93	0	0	0	1
T94	0	0	0	1
T95	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	3884	0	100
T20	3502	4	0	0
T21	1953	4	0	0
T50	926	0	0	0
T53	0	0	0	1
T54	0	45	0	1
T55	0	3	0	1
T56	0	44	0	1
T57	0	4	0	0
T86	0	32	0	1
T96	0	4	0	0
T97	0	3	0	1
T98	0	3	0	1
T99	1095	0	0	0
T100	5127	0	0	0
T101	1652	0	0	0
T102	1107	0	0	0
T103	3452	0	0	0
T104	1721	0	0	0
T105	1096	0	0	0
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	6463	0	89
T6	4670	0	0	0
T11	0	0	0	1
T14	1765	0	0	0
T15	2490	0	0	0
T16	44748	0	0	0
T28	20930	0	0	0
T29	1091	0	0	0
T30	2817	28	0	1
T31	0	3	0	1
T44	2154	0	0	0
T53	0	0	0	1
T58	0	4	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	0	3	0	1
T62	0	3	0	1
T67	1803	0	0	0
T74	1195	0	0	0
T99	0	3	0	1
T109	0	4	0	0
T110	0	4	0	0
T111	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	550199	0	276
T1	940	12	0	0
T2	1788	13	0	0
T3	2682	25	0	0
T4	761	288	0	0
T5	1965	637	0	0
T9	2116	185	0	0
T10	2083	1228	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T25	1012	53	0	0
T26	1349	11	0	0
T27	1110	1056	0	2
T42	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	2428	0	81
T12	0	0	0	1
T17	22527	0	0	0
T32	2273	0	0	0
T43	1367	1	0	0
T45	1290	0	0	0
T52	0	4	0	1
T53	0	3	0	1
T63	0	3	0	1
T64	0	0	0	1
T65	0	0	0	1
T68	19310	0	0	0
T75	1352	0	0	0
T78	1096	0	0	0
T114	0	4	0	1
T115	0	3	0	1
T116	0	4	0	1
T117	0	4	0	0
T118	0	4	0	0
T119	0	5	0	0
T120	1908	0	0	0
T121	1318	0	0	0
T122	1162	0	0	0
T123	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	9582372	0	0
T1	940	863	0	0
T2	1788	1694	0	0
T3	2682	2593	0	0
T4	761	628	0	0
T5	1965	1848	0	0
T9	2116	2033	0	0
T10	2083	1997	0	0
T25	1012	951	0	0
T26	1349	1277	0	0
T27	1110	1058	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9767389	142346	0	0
T4	761	360	0	0
T5	1965	230	0	0
T6	4670	0	0	0
T7	0	296	0	0
T9	2116	0	0	0
T10	2083	0	0	0
T16	0	15284	0	0
T17	0	7375	0	0
T25	1012	0	0	0
T26	1349	0	0	0
T27	1110	0	0	0
T30	2817	0	0	0
T43	0	630	0	0
T44	0	1136	0	0
T70	0	610	0	0
T73	1732	0	0	0
T77	0	182	0	0
T78	0	631	0	0