Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10295258	335153	0	0
boot_gen_cmd_rd_A	10295258	3519	0	0
boot_ins_cmd_rd_A	10295258	4275	0	0
ctrl_rd_A	10295258	4080	0	0
err_code_test_rd_A	10295258	4264	0	0
intr_enable_rd_A	10295258	9057	0	0
max_num_reqs_between_reseeds_rd_A	10295258	4353	0	0
regwen_rd_A	10295258	5068	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	335153	0	0
T39	134090	9228	0	0
T40	128311	5061	0	0
T41	304871	10521	0	0
T85	863	0	0	0
T131	2116	0	0	0
T132	26758	0	0	0
T133	82854	2783	0	0
T178	767	0	0	0
T241	0	11841	0	0
T242	0	21464	0	0
T243	0	5649	0	0
T244	0	9020	0	0
T245	0	6591	0	0
T246	0	6184	0	0
T247	1284	0	0	0
T248	13963	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	3519	0	0
T40	128311	158	0	0
T41	304871	214	0	0
T57	824	0	0	0
T85	863	0	0	0
T133	82854	0	0	0
T241	0	310	0	0
T244	0	355	0	0
T246	0	217	0	0
T249	0	285	0	0
T250	0	158	0	0
T251	0	558	0	0
T252	0	388	0	0
T253	0	136	0	0
T254	1388	0	0	0
T255	1069	0	0	0
T256	1865	0	0	0
T257	1510	0	0	0
T258	1729	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	4275	0	0
T40	128311	205	0	0
T41	304871	229	0	0
T57	824	0	0	0
T85	863	0	0	0
T133	82854	0	0	0
T241	0	415	0	0
T244	0	408	0	0
T246	0	295	0	0
T249	0	386	0	0
T250	0	172	0	0
T251	0	683	0	0
T252	0	398	0	0
T253	0	190	0	0
T254	1388	0	0	0
T255	1069	0	0	0
T256	1865	0	0	0
T257	1510	0	0	0
T258	1729	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	4080	0	0
T40	0	148	0	0
T41	0	189	0	0
T45	1290	0	0	0
T58	1113	0	0	0
T60	0	6	0	0
T69	14786	0	0	0
T76	1800	0	0	0
T78	1096	0	0	0
T102	0	5	0	0
T115	0	2	0	0
T121	1318	6	0	0
T122	1162	0	0	0
T127	2815	0	0	0
T137	0	40	0	0
T144	1872	0	0	0
T145	0	9	0	0
T241	0	440	0	0
T259	0	2	0	0
T260	1952	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	4264	0	0
T40	128311	233	0	0
T41	304871	200	0	0
T57	824	0	0	0
T85	863	0	0	0
T133	82854	0	0	0
T241	0	480	0	0
T244	0	467	0	0
T246	0	278	0	0
T249	0	341	0	0
T250	0	159	0	0
T251	0	559	0	0
T252	0	383	0	0
T253	0	153	0	0
T254	1388	0	0	0
T255	1069	0	0	0
T256	1865	0	0	0
T257	1510	0	0	0
T258	1729	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	9057	0	0
T40	0	386	0	0
T41	0	391	0	0
T54	2742	0	0	0
T62	847	0	0	0
T80	3204	0	0	0
T114	2484	0	0	0
T115	2633	0	0	0
T137	27968	172	0	0
T145	0	27	0	0
T147	709	0	0	0
T150	1916	0	0	0
T241	0	920	0	0
T261	0	7	0	0
T262	0	4	0	0
T263	0	37	0	0
T264	0	52	0	0
T265	0	32	0	0
T266	578	0	0	0
T267	862	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	4353	0	0
T40	128311	173	0	0
T41	304871	174	0	0
T57	824	0	0	0
T85	863	0	0	0
T133	82854	0	0	0
T241	0	360	0	0
T244	0	394	0	0
T246	0	251	0	0
T249	0	282	0	0
T250	0	161	0	0
T251	0	412	0	0
T252	0	267	0	0
T253	0	137	0	0
T254	1388	0	0	0
T255	1069	0	0	0
T256	1865	0	0	0
T257	1510	0	0	0
T258	1729	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10295258	5068	0	0
T40	128311	204	0	0
T41	304871	201	0	0
T57	824	0	0	0
T85	863	0	0	0
T133	82854	0	0	0
T241	0	397	0	0
T244	0	337	0	0
T246	0	233	0	0
T249	0	355	0	0
T250	0	195	0	0
T251	0	614	0	0
T252	0	388	0	0
T253	0	174	0	0
T254	1388	0	0	0
T255	1069	0	0	0
T256	1865	0	0	0
T257	1510	0	0	0
T258	1729	0	0	0