Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.23	93.97	97.02	91.28	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	94.04	99.92	92.75	82.54	91.28	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T30,T31

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T17,T18
1	0	Covered	T5,T6,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T9,T10,T29	Yes	T9,T10,T29	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T10,T8	Yes	T3,T10,T8	INPUT
edn_i[3].edn_req	Yes	Yes	T5,T15,T17	Yes	T5,T15,T17	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T26,T10	Yes	T3,T26,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T6,T10,T40	Yes	T6,T10,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T10,T20,T31	Yes	T10,T20,T31	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T10,T19	Yes	T1,T3,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T9,T10,T41	Yes	T9,T10,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T41,T40,T32	Yes	T41,T40,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T9,T10,T29	Yes	T9,T10,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T10,T8	Yes	T3,T10,T8	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T3,T10,T40	Yes	T3,T10,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T10,T40	Yes	T3,T10,T40	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T46,T47,T48	Yes	T44,T45,T49	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T5,T43,T44	Yes	T5,T43,T44	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T26,T10,T50	Yes	T26,T10,T50	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T51,T52,T46	Yes	T10,T50,T21	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T26,T10	Yes	T3,T26,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T6,T10,T53	Yes	T6,T10,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T54,T55,T56	Yes	T10,T53,T57	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T6,T10,T40	Yes	T6,T10,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T10,T31,T40	Yes	T10,T20,T31	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T10,T58,T59	Yes	T10,T22,T60	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T10,T20,T31	Yes	T10,T20,T31	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T9,T10	Yes	T3,T10,T61	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T10,T62	Yes	T3,T10,T20	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T63,T57,T64	Yes	T63,T57,T64	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T25,T9,T30	Yes	T25,T9,T30	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T25,T6	Yes	T5,T25,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T25,T9,T30	Yes	T25,T9,T30	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T25,T6	Yes	T5,T25,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T61,T65	Yes	T4,T61,T65	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	11812791	11634995	0	0
CsrngAppIfOut_A	11812791	11634995	0	0
FpvSecCmCntAlertCheck_A	11812791	112	0	0
FpvSecCmGenCmdFifoRptrCheck_A	11812791	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	11812791	70	0	0
FpvSecCmMainFsmCheck_A	11812791	70	0	0
FpvSecCmRegWeOnehotCheck_A	11812791	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	11812791	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	11812791	70	0	0
IntrEdnCmdReqDoneKnownO_A	11812791	11634995	0	0
TlAReadyKnownO_A	11812791	11634995	0	0
TlDValidKnownO_A	11812791	11634995	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	11812791	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[0].EdnDataStable_A	11812791	66688	0	413
gen_edn_if_asserts[0].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[1].EdnDataStable_A	11812791	8574	0	138
gen_edn_if_asserts[1].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[2].EdnDataStable_A	11812791	2039	0	107
gen_edn_if_asserts[2].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[3].EdnDataStable_A	11812791	4332	0	113
gen_edn_if_asserts[3].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[4].EdnDataStable_A	11812791	5157	0	85
gen_edn_if_asserts[4].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[5].EdnDataStable_A	11812791	2450	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	11812791	145087	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	11812791	544366	0	270
gen_edn_if_asserts[6].EdnDataStable_A	11812791	3414	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	11812791	11634995	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	11812791	145087	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	112	0	0
T6	2264	1	0	0
T7	1098	0	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	1	0	0
T15	0	10	0	0
T16	1766	0	0	0
T17	0	20	0	0
T18	0	10	0	0
T19	744	0	0	0
T27	1062	0	0	0
T29	741	0	0	0
T30	2491	0	0	0
T63	0	1	0	0
T66	0	10	0	0
T67	0	1	0	0
T68	0	20	0	0
T69	0	1	0	0
T70	1493	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	70	0	0
T15	24923	10	0	0
T17	46504	20	0	0
T18	0	10	0	0
T36	863	0	0	0
T50	1165	0	0	0
T53	2253	0	0	0
T57	2300	0	0	0
T63	1130	0	0	0
T65	12722	0	0	0
T66	0	10	0	0
T68	0	20	0	0
T71	995	0	0	0
T72	1875	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	66688	0	413
T1	1609	3	0	1
T2	1035	3	0	1
T3	3006	49	0	1
T4	6105	3	0	0
T5	1305	0	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	0	28	0	1
T16	1766	0	0	0
T19	0	1	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	0	3	0	1
T28	0	3	0	1
T30	0	4	0	1
T61	0	0	0	1
T70	0	3	0	1
T75	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	8574	0	138
T7	1098	0	0	0
T9	2258	4	0	1
T10	3605	3	0	1
T19	744	0	0	0
T20	2153	0	0	0
T27	1062	0	0	0
T29	741	3	0	1
T30	2491	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T40	0	26	0	1
T41	0	4	0	0
T42	0	3	0	1
T56	0	0	0	1
T70	1493	0	0	0
T73	1480	0	0	0
T76	0	4	0	1
T77	0	4	0	0
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	2039	0	107
T3	3006	43	0	1
T4	6105	0	0	0
T5	1305	0	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	0	58	0	1
T16	1766	0	0	0
T24	0	4	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T40	0	42	0	1
T46	0	0	0	1
T56	0	39	0	1
T58	0	30	0	1
T70	1493	0	0	0
T78	0	3	0	1
T79	0	15	0	1
T81	0	4	0	1
T82	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	4332	0	113
T5	1305	1	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T16	1766	0	0	0
T19	744	0	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T43	0	4	0	0
T44	0	3	0	1
T45	0	4	0	1
T46	0	0	0	1
T49	0	4	0	0
T58	0	0	0	1
T70	1493	0	0	0
T78	0	3	0	1
T83	0	4	0	1
T84	0	3	0	1
T85	0	4	0	0
T86	0	1	0	0
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	5157	0	85
T3	3006	3	0	1
T4	6105	0	0	0
T5	1305	0	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	0	3	0	1
T16	1766	0	0	0
T21	0	4	0	0
T25	1151	0	0	0
T26	1057	4	0	0
T27	1062	0	0	0
T34	0	1	0	0
T46	0	0	0	1
T50	0	3	0	1
T51	0	1	0	0
T58	0	0	0	1
T70	1493	0	0	0
T77	0	1	0	0
T78	0	0	0	1
T81	0	4	0	0
T89	0	0	0	1
T90	0	3	0	1
T91	0	0	0	1
T92	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	2450	0	92
T6	2264	1	0	0
T7	1098	0	0	0
T9	2258	0	0	0
T10	3605	3	0	1
T16	1766	0	0	0
T19	744	0	0	0
T27	1062	0	0	0
T29	741	0	0	0
T30	2491	0	0	0
T40	0	3	0	1
T46	0	0	0	1
T53	0	4	0	0
T56	0	0	0	1
T57	0	4	0	1
T58	0	0	0	1
T60	0	1	0	0
T70	1493	0	0	0
T78	0	3	0	1
T93	0	4	0	0
T94	0	4	0	1
T95	0	1	0	0
T96	0	0	0	1
T97	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	544366	0	270
T1	1609	26	0	0
T2	1035	12	0	0
T3	3006	18	0	0
T4	6105	1062	0	0
T5	1305	566	0	0
T6	2264	1330	0	0
T9	2258	313	0	0
T15	0	0	0	2
T16	1766	1011	0	0
T17	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T23	0	0	0	2
T25	1151	1067	0	2
T26	1057	104	0	0
T53	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	3414	0	75
T7	1098	0	0	0
T8	1230	0	0	0
T10	3605	387	0	1
T19	744	0	0	0
T20	2153	4	0	0
T22	0	4	0	0
T23	0	4	0	0
T28	984	0	0	0
T29	741	0	0	0
T30	2491	0	0	0
T31	0	4	0	1
T40	0	3	0	1
T46	0	0	0	1
T58	0	0	0	1
T60	0	4	0	0
T73	1480	0	0	0
T75	1137	0	0	0
T78	0	3	0	1
T98	0	1	0	0
T99	0	3	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	11634995	0	0
T1	1609	1522	0	0
T2	1035	966	0	0
T3	3006	2912	0	0
T4	6105	5898	0	0
T5	1305	1132	0	0
T6	2264	2097	0	0
T9	2258	2172	0	0
T16	1766	1608	0	0
T25	1151	1069	0	0
T26	1057	963	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11812791	145087	0	0
T5	1305	22	0	0
T6	2264	1114	0	0
T7	0	229	0	0
T8	0	392	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T14	0	210	0	0
T15	0	9309	0	0
T16	1766	1072	0	0
T19	744	13	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T36	0	23	0	0
T63	0	631	0	0
T70	1493	0	0	0