Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12307411	409051	0	0
boot_gen_cmd_rd_A	12307411	2651	0	0
boot_ins_cmd_rd_A	12307411	2692	0	0
ctrl_rd_A	12307411	2819	0	0
err_code_test_rd_A	12307411	2751	0	0
intr_enable_rd_A	12307411	5545	0	0
max_num_reqs_between_reseeds_rd_A	12307411	3432	0	0
regwen_rd_A	12307411	3541	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	409051	0	0
T37	166588	7300	0	0
T38	0	4824	0	0
T39	0	7497	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T225	0	10371	0	0
T226	0	9948	0	0
T227	0	12955	0	0
T228	0	14181	0	0
T229	0	5727	0	0
T230	0	8296	0	0
T231	0	18309	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	2651	0	0
T37	166588	137	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T229	0	121	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0
T235	0	516	0	0
T236	0	224	0	0
T237	0	441	0	0
T238	0	213	0	0
T239	0	630	0	0
T240	0	24	0	0
T241	0	8	0	0
T242	0	3	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	2692	0	0
T37	166588	126	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T229	0	86	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0
T235	0	525	0	0
T236	0	170	0	0
T237	0	419	0	0
T238	0	174	0	0
T239	0	666	0	0
T240	0	46	0	0
T241	0	9	0	0
T243	0	36	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	2819	0	0
T4	6105	4	0	0
T5	1305	0	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T16	1766	0	0	0
T21	0	3	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T37	0	143	0	0
T54	0	7	0	0
T70	1493	0	0	0
T135	0	12	0	0
T177	0	7	0	0
T229	0	121	0	0
T244	0	2	0	0
T245	0	6	0	0
T246	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	2751	0	0
T37	166588	117	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T229	0	79	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0
T235	0	581	0	0
T236	0	235	0	0
T237	0	546	0	0
T238	0	244	0	0
T239	0	614	0	0
T240	0	60	0	0
T241	0	4	0	0
T242	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	5545	0	0
T4	6105	53	0	0
T5	1305	0	0	0
T6	2264	0	0	0
T9	2258	0	0	0
T10	3605	0	0	0
T16	1766	0	0	0
T25	1151	0	0	0
T26	1057	0	0	0
T27	1062	0	0	0
T37	0	170	0	0
T70	1493	0	0	0
T229	0	205	0	0
T244	0	28	0	0
T245	0	38	0	0
T246	0	13	0	0
T247	0	1	0	0
T248	0	56	0	0
T249	0	72	0	0
T250	0	42	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	3432	0	0
T37	166588	118	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T229	0	129	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0
T235	0	460	0	0
T236	0	170	0	0
T237	0	479	0	0
T238	0	228	0	0
T239	0	675	0	0
T240	0	52	0	0
T241	0	4	0	0
T242	0	74	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12307411	3541	0	0
T37	166588	151	0	0
T79	3438	0	0	0
T86	2225	0	0	0
T130	2025	0	0	0
T134	727	0	0	0
T181	870	0	0	0
T208	2922	0	0	0
T229	0	123	0	0
T232	1204	0	0	0
T233	1744	0	0	0
T234	30356	0	0	0
T235	0	460	0	0
T236	0	164	0	0
T237	0	471	0	0
T238	0	288	0	0
T239	0	710	0	0
T240	0	44	0	0
T241	0	13	0	0
T242	0	78	0	0