Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12359530	422614	0	0
boot_gen_cmd_rd_A	12359530	3590	0	0
boot_ins_cmd_rd_A	12359530	4053	0	0
ctrl_rd_A	12359530	3786	0	0
err_code_test_rd_A	12359530	3906	0	0
intr_enable_rd_A	12359530	8526	0	0
max_num_reqs_between_reseeds_rd_A	12359530	4046	0	0
regwen_rd_A	12359530	4585	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	422614	0	0
T38	119509	4654	0	0
T39	0	10233	0	0
T40	0	6968	0	0
T76	2981	0	0	0
T103	911	0	0	0
T142	1411	0	0	0
T236	0	8822	0	0
T237	0	10516	0	0
T238	0	4497	0	0
T239	0	19431	0	0
T240	0	12710	0	0
T241	0	19202	0	0
T242	0	2921	0	0
T243	3093	0	0	0
T244	19063	0	0	0
T245	8862	0	0	0
T246	1611	0	0	0
T247	1573	0	0	0
T248	2310	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	3590	0	0
T178	2198	0	0	0
T196	1098	0	0	0
T236	250011	162	0	0
T238	0	154	0	0
T242	0	126	0	0
T249	0	171	0	0
T250	0	141	0	0
T251	0	276	0	0
T252	0	296	0	0
T253	0	197	0	0
T254	0	253	0	0
T255	0	270	0	0
T256	1747	0	0	0
T257	2838	0	0	0
T258	854	0	0	0
T259	1398	0	0	0
T260	1295	0	0	0
T261	13915	0	0	0
T262	868	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	4053	0	0
T178	2198	0	0	0
T196	1098	0	0	0
T236	250011	156	0	0
T238	0	195	0	0
T242	0	137	0	0
T249	0	196	0	0
T250	0	172	0	0
T251	0	271	0	0
T252	0	370	0	0
T253	0	200	0	0
T254	0	350	0	0
T255	0	233	0	0
T256	1747	0	0	0
T257	2838	0	0	0
T258	854	0	0	0
T259	1398	0	0	0
T260	1295	0	0	0
T261	13915	0	0	0
T262	868	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	3786	0	0
T16	4826	0	0	0
T17	43281	0	0	0
T18	25395	0	0	0
T22	0	4	0	0
T30	881	2	0	0
T47	0	7	0	0
T56	27185	2	0	0
T65	1314	0	0	0
T70	1046	1	0	0
T82	878	0	0	0
T83	1050	0	0	0
T84	1214	0	0	0
T122	0	4	0	0
T124	0	3	0	0
T129	0	4	0	0
T263	0	9	0	0
T264	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	3906	0	0
T178	2198	0	0	0
T196	1098	0	0	0
T236	250011	143	0	0
T238	0	151	0	0
T242	0	107	0	0
T249	0	163	0	0
T250	0	206	0	0
T251	0	301	0	0
T252	0	381	0	0
T253	0	221	0	0
T254	0	302	0	0
T255	0	318	0	0
T256	1747	0	0	0
T257	2838	0	0	0
T258	854	0	0	0
T259	1398	0	0	0
T260	1295	0	0	0
T261	13915	0	0	0
T262	868	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	8526	0	0
T16	4826	0	0	0
T17	43281	0	0	0
T18	25395	0	0	0
T30	881	0	0	0
T43	2196	0	0	0
T52	2292	0	0	0
T56	27185	132	0	0
T62	2489	0	0	0
T83	1050	0	0	0
T84	1214	0	0	0
T112	0	49	0	0
T114	0	88	0	0
T120	0	84	0	0
T264	0	38	0	0
T265	0	55	0	0
T266	0	55	0	0
T267	0	34	0	0
T268	0	71	0	0
T269	0	59	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	4046	0	0
T178	2198	0	0	0
T196	1098	0	0	0
T236	250011	103	0	0
T238	0	274	0	0
T242	0	109	0	0
T249	0	166	0	0
T250	0	153	0	0
T251	0	254	0	0
T252	0	322	0	0
T253	0	201	0	0
T254	0	192	0	0
T255	0	303	0	0
T256	1747	0	0	0
T257	2838	0	0	0
T258	854	0	0	0
T259	1398	0	0	0
T260	1295	0	0	0
T261	13915	0	0	0
T262	868	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12359530	4585	0	0
T178	2198	0	0	0
T196	1098	0	0	0
T236	250011	163	0	0
T238	0	258	0	0
T242	0	154	0	0
T249	0	148	0	0
T250	0	199	0	0
T251	0	262	0	0
T252	0	418	0	0
T253	0	227	0	0
T254	0	300	0	0
T255	0	242	0	0
T256	1747	0	0	0
T257	2838	0	0	0
T258	854	0	0	0
T259	1398	0	0	0
T260	1295	0	0	0
T261	13915	0	0	0
T262	868	0	0	0