Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.40	98.23	93.97	97.07	93.02	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	94.38	99.92	92.75	82.84	93.02	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T19,T12

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T20
1	0	Covered	T4,T5,T32

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T37	Yes	T3,T4,T37	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T28,T41,T17	Yes	T28,T41,T17	INPUT
edn_i[2].edn_req	Yes	Yes	T41,T17,T30	Yes	T41,T17,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T32,T41,T17	Yes	T32,T41,T17	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T19,T41	Yes	T10,T19,T41	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T24,T11	Yes	T4,T24,T11	INPUT
edn_i[6].edn_req	Yes	Yes	T41,T17,T18	Yes	T41,T17,T18	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T25,T27	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T29,T31,T42	Yes	T25,T27,T29	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T28,T41,T43	Yes	T28,T41,T16	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T23,T7,T44	Yes	T41,T16,T45	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T28,T41,T16	Yes	T28,T41,T16	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T41,T46,T47	Yes	T41,T46,T47	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T41,T47,T48	Yes	T41,T46,T47	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T41,T30,T46	Yes	T41,T30,T46	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T49,T46,T50	Yes	T49,T21,T23	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T49,T46,T51	Yes	T41,T49,T21	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T41,T49,T21	Yes	T41,T49,T21	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T10,T19,T52	Yes	T10,T19,T41	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T53,T46,T50	Yes	T10,T41,T52	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T19,T41	Yes	T10,T19,T41	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T24,T11	Yes	T4,T24,T11	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T4,T23,T50	Yes	T4,T24,T11	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T24,T11	Yes	T4,T24,T11	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T41,T23,T46	Yes	T41,T23,T46	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T33,T23	Yes	T41,T33,T23	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T41,T33,T23	Yes	T41,T33,T23	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T10	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T25,T29,T11	Yes	T28,T29,T11	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T10,T29,T41	Yes	T25,T28,T29	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T25,T54,T55	Yes	T25,T54,T55	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T25,T26,T19	Yes	T25,T26,T19	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T25,T26,T19	Yes	T25,T26,T19	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T42,T56	Yes	T6,T42,T56	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T31	Yes	T4,T6,T31	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	11881186	11681859	0	0
CsrngAppIfOut_A	11881186	11681859	0	0
FpvSecCmCntAlertCheck_A	11881186	139	0	0
FpvSecCmGenCmdFifoRptrCheck_A	11881186	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	11881186	90	0	0
FpvSecCmMainFsmCheck_A	11881186	90	0	0
FpvSecCmRegWeOnehotCheck_A	11881186	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	11881186	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	11881186	90	0	0
IntrEdnCmdReqDoneKnownO_A	11881186	11681859	0	0
TlAReadyKnownO_A	11881186	11681859	0	0
TlDValidKnownO_A	11881186	11681859	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	11881186	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[0].EdnDataStable_A	11881186	68757	0	430
gen_edn_if_asserts[0].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[1].EdnDataStable_A	11881186	4551	0	142
gen_edn_if_asserts[1].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[2].EdnDataStable_A	11881186	2913	0	113
gen_edn_if_asserts[2].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[3].EdnDataStable_A	11881186	4576	0	111
gen_edn_if_asserts[3].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[4].EdnDataStable_A	11881186	2344	0	99
gen_edn_if_asserts[4].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[5].EdnDataStable_A	11881186	4657	0	83
gen_edn_if_asserts[5].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	11881186	165875	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	11881186	566759	0	288
gen_edn_if_asserts[6].EdnDataStable_A	11881186	4276	0	94
gen_edn_if_asserts[6].EdnEndPointOut_A	11881186	11681859	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	11881186	165875	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	139	0	0
T5	1783	1	0	0
T6	26706	0	0	0
T7	0	1	0	0
T10	2747	0	0	0
T17	0	20	0	0
T18	0	10	0	0
T20	0	20	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T29	1539	0	0	0
T37	1266	0	0	0
T57	0	1	0	0
T58	0	20	0	0
T59	0	1	0	0
T60	0	20	0	0
T61	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	90	0	0
T16	4826	0	0	0
T17	43281	20	0	0
T18	25395	10	0	0
T20	0	20	0	0
T30	881	0	0	0
T43	2196	0	0	0
T45	1747	0	0	0
T52	2292	0	0	0
T53	1180	0	0	0
T58	0	20	0	0
T60	0	20	0	0
T62	2489	0	0	0
T63	631	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	68757	0	430
T1	1479	3	0	1
T2	904	3	0	1
T3	3835	3	0	1
T4	889	0	0	0
T5	1783	0	0	0
T6	0	3	0	0
T10	2747	0	0	0
T11	0	1	0	0
T24	882	0	0	0
T25	2039	8	0	1
T26	1178	0	0	0
T27	1382	3	0	1
T29	0	48	0	1
T31	0	1	0	0
T37	0	3	0	1
T41	0	0	0	1
T67	0	0	0	1
T68	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	4551	0	142
T11	3567	0	0	0
T16	0	4	0	0
T19	1951	0	0	0
T23	0	196	0	1
T28	809	4	0	0
T29	1539	0	0	0
T31	1942	0	0	0
T32	1800	0	0	0
T41	1812	3	0	1
T43	0	1	0	0
T45	0	4	0	0
T50	0	3	0	1
T57	0	1	0	0
T59	0	1	0	0
T64	1295	0	0	0
T67	1089	0	0	0
T68	1312	0	0	0
T71	0	3	0	1
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	2913	0	113
T12	1809	0	0	0
T30	0	1	0	0
T41	1812	19	0	1
T42	7536	0	0	0
T46	0	3	0	1
T47	0	4	0	0
T48	0	25	0	1
T56	27185	0	0	0
T65	1314	0	0	0
T69	2147	0	0	0
T70	1046	0	0	0
T72	0	3	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1
T78	0	1	0	0
T79	0	3	0	1
T80	0	1	0	0
T81	0	4	0	0
T82	878	0	0	0
T83	1050	0	0	0
T84	1214	0	0	0
T85	0	0	0	1
T86	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	4576	0	111
T12	1809	0	0	0
T21	0	4	0	0
T23	0	3	0	1
T41	1812	3	0	1
T42	7536	0	0	0
T46	0	15	0	1
T48	0	3	0	1
T49	0	16	0	1
T50	0	13	0	1
T56	27185	0	0	0
T65	1314	0	0	0
T69	2147	0	0	0
T70	1046	0	0	0
T72	0	0	0	1
T79	0	0	0	1
T82	878	0	0	0
T83	1050	0	0	0
T84	1214	0	0	0
T87	0	4	0	0
T88	0	1	0	0
T89	0	4	0	1
T90	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	2344	0	99
T6	26706	0	0	0
T10	2747	4	0	0
T19	1951	4	0	1
T23	0	3	0	1
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T29	1539	0	0	0
T32	1800	0	0	0
T37	1266	0	0	0
T41	0	3	0	1
T45	0	1	0	0
T46	0	61	0	1
T50	0	25	0	1
T52	0	4	0	1
T53	0	4	0	0
T55	0	4	0	1
T79	0	0	0	1
T91	0	0	0	1
T92	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	4657	0	83
T6	26706	0	0	0
T10	2747	0	0	0
T11	0	4	0	0
T19	1951	0	0	0
T22	0	4	0	0
T23	0	8	0	1
T24	882	3	0	1
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T29	1539	0	0	0
T37	1266	0	0	0
T48	0	3	0	1
T50	0	19	0	1
T54	0	4	0	1
T72	0	0	0	1
T76	0	0	0	1
T93	0	3	0	1
T94	0	3	0	1
T95	0	4	0	0
T96	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	566759	0	288
T1	1479	16	0	0
T2	904	11	0	0
T3	3835	18	0	0
T4	889	39	0	0
T5	1783	1012	0	0
T10	2747	1314	0	2
T11	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T24	882	75	0	0
T25	2039	133	0	0
T26	1178	1089	0	2
T27	1382	173	0	0
T45	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	4276	0	94
T12	1809	0	0	0
T23	0	47	0	1
T33	0	1	0	0
T41	1812	51	0	1
T42	7536	0	0	0
T46	0	56	0	1
T56	27185	0	0	0
T65	1314	0	0	0
T69	2147	0	0	0
T70	1046	0	0	0
T73	0	3	0	1
T76	0	0	0	1
T77	0	0	0	1
T82	878	0	0	0
T83	1050	0	0	0
T84	1214	0	0	0
T97	0	4	0	0
T98	0	1	0	0
T99	0	3	0	1
T100	0	4	0	1
T101	0	4	0	0
T102	0	0	0	1
T103	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	11681859	0	0
T1	1479	1387	0	0
T2	904	818	0	0
T3	3835	3741	0	0
T4	889	770	0	0
T5	1783	1604	0	0
T10	2747	2658	0	0
T24	882	829	0	0
T25	2039	1962	0	0
T26	1178	1091	0	0
T27	1382	1295	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11881186	165875	0	0
T4	889	380	0	0
T5	1783	1074	0	0
T6	26706	0	0	0
T10	2747	0	0	0
T17	0	16227	0	0
T18	0	11024	0	0
T24	882	0	0	0
T25	2039	0	0	0
T26	1178	0	0	0
T27	1382	0	0	0
T28	809	0	0	0
T30	0	32	0	0
T31	0	7	0	0
T32	0	1112	0	0
T37	1266	0	0	0
T43	0	1136	0	0
T69	0	1110	0	0
T70	0	532	0	0