Line Coverage for Module :
edn_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 152 | 152 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 333 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 355 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 370 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 386 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 589 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 603 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 856 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 870 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 876 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 890 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 930 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1352 | 1 | 1 | 100.00 |
| ALWAYS | 1386 | 19 | 19 | 100.00 |
| CONT_ASSIGN | 1407 | 1 | 1 | 100.00 |
| ALWAYS | 1411 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1433 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1435 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1437 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1438 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1440 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1442 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1443 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1445 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1448 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1452 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1453 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1455 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1458 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1460 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1462 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1464 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1465 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1467 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1468 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1471 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1473 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1476 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1480 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1482 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1483 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1485 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1487 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1489 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1491 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1493 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1495 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1496 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1498 | 1 | 1 | 100.00 |
| ALWAYS | 1502 | 19 | 19 | 100.00 |
| ALWAYS | 1525 | 46 | 46 | 100.00 |
| CONT_ASSIGN | 1636 | 0 | 0 | |
| CONT_ASSIGN | 1644 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1645 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T17 T18 T20
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T38 T39 T40
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic intr_state_we;
125 logic intr_state_edn_cmd_req_done_qs;
126 logic intr_state_edn_cmd_req_done_wd;
127 logic intr_state_edn_fatal_err_qs;
128 logic intr_state_edn_fatal_err_wd;
129 logic intr_enable_we;
130 logic intr_enable_edn_cmd_req_done_qs;
131 logic intr_enable_edn_cmd_req_done_wd;
132 logic intr_enable_edn_fatal_err_qs;
133 logic intr_enable_edn_fatal_err_wd;
134 logic intr_test_we;
135 logic intr_test_edn_cmd_req_done_wd;
136 logic intr_test_edn_fatal_err_wd;
137 logic alert_test_we;
138 logic alert_test_recov_alert_wd;
139 logic alert_test_fatal_alert_wd;
140 logic regwen_we;
141 logic regwen_qs;
142 logic regwen_wd;
143 logic ctrl_we;
144 logic [3:0] ctrl_edn_enable_qs;
145 logic [3:0] ctrl_edn_enable_wd;
146 logic [3:0] ctrl_boot_req_mode_qs;
147 logic [3:0] ctrl_boot_req_mode_wd;
148 logic [3:0] ctrl_auto_req_mode_qs;
149 logic [3:0] ctrl_auto_req_mode_wd;
150 logic [3:0] ctrl_cmd_fifo_rst_qs;
151 logic [3:0] ctrl_cmd_fifo_rst_wd;
152 logic boot_ins_cmd_we;
153 logic [31:0] boot_ins_cmd_qs;
154 logic [31:0] boot_ins_cmd_wd;
155 logic boot_gen_cmd_we;
156 logic [31:0] boot_gen_cmd_qs;
157 logic [31:0] boot_gen_cmd_wd;
158 logic sw_cmd_req_we;
159 logic [31:0] sw_cmd_req_wd;
160 logic sw_cmd_sts_cmd_reg_rdy_qs;
161 logic sw_cmd_sts_cmd_rdy_qs;
162 logic sw_cmd_sts_cmd_ack_qs;
163 logic [2:0] sw_cmd_sts_cmd_sts_qs;
164 logic hw_cmd_sts_boot_mode_qs;
165 logic hw_cmd_sts_auto_mode_qs;
166 logic [3:0] hw_cmd_sts_cmd_type_qs;
167 logic hw_cmd_sts_cmd_ack_qs;
168 logic [2:0] hw_cmd_sts_cmd_sts_qs;
169 logic reseed_cmd_we;
170 logic [31:0] reseed_cmd_wd;
171 logic generate_cmd_we;
172 logic [31:0] generate_cmd_wd;
173 logic max_num_reqs_between_reseeds_we;
174 logic [31:0] max_num_reqs_between_reseeds_qs;
175 logic [31:0] max_num_reqs_between_reseeds_wd;
176 logic recov_alert_sts_we;
177 logic recov_alert_sts_edn_enable_field_alert_qs;
178 logic recov_alert_sts_edn_enable_field_alert_wd;
179 logic recov_alert_sts_boot_req_mode_field_alert_qs;
180 logic recov_alert_sts_boot_req_mode_field_alert_wd;
181 logic recov_alert_sts_auto_req_mode_field_alert_qs;
182 logic recov_alert_sts_auto_req_mode_field_alert_wd;
183 logic recov_alert_sts_cmd_fifo_rst_field_alert_qs;
184 logic recov_alert_sts_cmd_fifo_rst_field_alert_wd;
185 logic recov_alert_sts_edn_bus_cmp_alert_qs;
186 logic recov_alert_sts_edn_bus_cmp_alert_wd;
187 logic recov_alert_sts_csrng_ack_err_qs;
188 logic recov_alert_sts_csrng_ack_err_wd;
189 logic err_code_sfifo_rescmd_err_qs;
190 logic err_code_sfifo_gencmd_err_qs;
191 logic err_code_edn_ack_sm_err_qs;
192 logic err_code_edn_main_sm_err_qs;
193 logic err_code_edn_cntr_err_qs;
194 logic err_code_fifo_write_err_qs;
195 logic err_code_fifo_read_err_qs;
196 logic err_code_fifo_state_err_qs;
197 logic err_code_test_we;
198 logic [4:0] err_code_test_qs;
199 logic [4:0] err_code_test_wd;
200 logic [8:0] main_sm_state_qs;
201
202 // Register instances
203 // R[intr_state]: V(False)
204 // F[edn_cmd_req_done]: 0:0
205 prim_subreg #(
206 .DW (1),
207 .SwAccess(prim_subreg_pkg::SwAccessW1C),
208 .RESVAL (1'h0),
209 .Mubi (1'b0)
210 ) u_intr_state_edn_cmd_req_done (
211 .clk_i (clk_i),
212 .rst_ni (rst_ni),
213
214 // from register interface
215 .we (intr_state_we),
216 .wd (intr_state_edn_cmd_req_done_wd),
217
218 // from internal hardware
219 .de (hw2reg.intr_state.edn_cmd_req_done.de),
220 .d (hw2reg.intr_state.edn_cmd_req_done.d),
221
222 // to internal hardware
223 .qe (),
224 .q (reg2hw.intr_state.edn_cmd_req_done.q),
225 .ds (),
226
227 // to register interface (read)
228 .qs (intr_state_edn_cmd_req_done_qs)
229 );
230
231 // F[edn_fatal_err]: 1:1
232 prim_subreg #(
233 .DW (1),
234 .SwAccess(prim_subreg_pkg::SwAccessW1C),
235 .RESVAL (1'h0),
236 .Mubi (1'b0)
237 ) u_intr_state_edn_fatal_err (
238 .clk_i (clk_i),
239 .rst_ni (rst_ni),
240
241 // from register interface
242 .we (intr_state_we),
243 .wd (intr_state_edn_fatal_err_wd),
244
245 // from internal hardware
246 .de (hw2reg.intr_state.edn_fatal_err.de),
247 .d (hw2reg.intr_state.edn_fatal_err.d),
248
249 // to internal hardware
250 .qe (),
251 .q (reg2hw.intr_state.edn_fatal_err.q),
252 .ds (),
253
254 // to register interface (read)
255 .qs (intr_state_edn_fatal_err_qs)
256 );
257
258
259 // R[intr_enable]: V(False)
260 // F[edn_cmd_req_done]: 0:0
261 prim_subreg #(
262 .DW (1),
263 .SwAccess(prim_subreg_pkg::SwAccessRW),
264 .RESVAL (1'h0),
265 .Mubi (1'b0)
266 ) u_intr_enable_edn_cmd_req_done (
267 .clk_i (clk_i),
268 .rst_ni (rst_ni),
269
270 // from register interface
271 .we (intr_enable_we),
272 .wd (intr_enable_edn_cmd_req_done_wd),
273
274 // from internal hardware
275 .de (1'b0),
276 .d ('0),
277
278 // to internal hardware
279 .qe (),
280 .q (reg2hw.intr_enable.edn_cmd_req_done.q),
281 .ds (),
282
283 // to register interface (read)
284 .qs (intr_enable_edn_cmd_req_done_qs)
285 );
286
287 // F[edn_fatal_err]: 1:1
288 prim_subreg #(
289 .DW (1),
290 .SwAccess(prim_subreg_pkg::SwAccessRW),
291 .RESVAL (1'h0),
292 .Mubi (1'b0)
293 ) u_intr_enable_edn_fatal_err (
294 .clk_i (clk_i),
295 .rst_ni (rst_ni),
296
297 // from register interface
298 .we (intr_enable_we),
299 .wd (intr_enable_edn_fatal_err_wd),
300
301 // from internal hardware
302 .de (1'b0),
303 .d ('0),
304
305 // to internal hardware
306 .qe (),
307 .q (reg2hw.intr_enable.edn_fatal_err.q),
308 .ds (),
309
310 // to register interface (read)
311 .qs (intr_enable_edn_fatal_err_qs)
312 );
313
314
315 // R[intr_test]: V(True)
316 logic intr_test_qe;
317 logic [1:0] intr_test_flds_we;
318 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T6 T42 T56
319 // F[edn_cmd_req_done]: 0:0
320 prim_subreg_ext #(
321 .DW (1)
322 ) u_intr_test_edn_cmd_req_done (
323 .re (1'b0),
324 .we (intr_test_we),
325 .wd (intr_test_edn_cmd_req_done_wd),
326 .d ('0),
327 .qre (),
328 .qe (intr_test_flds_we[0]),
329 .q (reg2hw.intr_test.edn_cmd_req_done.q),
330 .ds (),
331 .qs ()
332 );
333 1/1 assign reg2hw.intr_test.edn_cmd_req_done.qe = intr_test_qe;
Tests: T6 T42 T56
334
335 // F[edn_fatal_err]: 1:1
336 prim_subreg_ext #(
337 .DW (1)
338 ) u_intr_test_edn_fatal_err (
339 .re (1'b0),
340 .we (intr_test_we),
341 .wd (intr_test_edn_fatal_err_wd),
342 .d ('0),
343 .qre (),
344 .qe (intr_test_flds_we[1]),
345 .q (reg2hw.intr_test.edn_fatal_err.q),
346 .ds (),
347 .qs ()
348 );
349 1/1 assign reg2hw.intr_test.edn_fatal_err.qe = intr_test_qe;
Tests: T6 T42 T56
350
351
352 // R[alert_test]: V(True)
353 logic alert_test_qe;
354 logic [1:0] alert_test_flds_we;
355 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T26 T64 T65
356 // F[recov_alert]: 0:0
357 prim_subreg_ext #(
358 .DW (1)
359 ) u_alert_test_recov_alert (
360 .re (1'b0),
361 .we (alert_test_we),
362 .wd (alert_test_recov_alert_wd),
363 .d ('0),
364 .qre (),
365 .qe (alert_test_flds_we[0]),
366 .q (reg2hw.alert_test.recov_alert.q),
367 .ds (),
368 .qs ()
369 );
370 1/1 assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
Tests: T26 T64 T65
371
372 // F[fatal_alert]: 1:1
373 prim_subreg_ext #(
374 .DW (1)
375 ) u_alert_test_fatal_alert (
376 .re (1'b0),
377 .we (alert_test_we),
378 .wd (alert_test_fatal_alert_wd),
379 .d ('0),
380 .qre (),
381 .qe (alert_test_flds_we[1]),
382 .q (reg2hw.alert_test.fatal_alert.q),
383 .ds (),
384 .qs ()
385 );
386 1/1 assign reg2hw.alert_test.fatal_alert.qe = alert_test_qe;
Tests: T26 T64 T65
387
388
389 // R[regwen]: V(False)
390 prim_subreg #(
391 .DW (1),
392 .SwAccess(prim_subreg_pkg::SwAccessW0C),
393 .RESVAL (1'h1),
394 .Mubi (1'b0)
395 ) u_regwen (
396 .clk_i (clk_i),
397 .rst_ni (rst_ni),
398
399 // from register interface
400 .we (regwen_we),
401 .wd (regwen_wd),
402
403 // from internal hardware
404 .de (1'b0),
405 .d ('0),
406
407 // to internal hardware
408 .qe (),
409 .q (),
410 .ds (),
411
412 // to register interface (read)
413 .qs (regwen_qs)
414 );
415
416
417 // R[ctrl]: V(False)
418 // Create REGWEN-gated WE signal
419 logic ctrl_gated_we;
420 1/1 assign ctrl_gated_we = ctrl_we & regwen_qs;
Tests: T1 T2 T3
421 // F[edn_enable]: 3:0
422 prim_subreg #(
423 .DW (4),
424 .SwAccess(prim_subreg_pkg::SwAccessRW),
425 .RESVAL (4'h9),
426 .Mubi (1'b1)
427 ) u_ctrl_edn_enable (
428 .clk_i (clk_i),
429 .rst_ni (rst_ni),
430
431 // from register interface
432 .we (ctrl_gated_we),
433 .wd (ctrl_edn_enable_wd),
434
435 // from internal hardware
436 .de (1'b0),
437 .d ('0),
438
439 // to internal hardware
440 .qe (),
441 .q (reg2hw.ctrl.edn_enable.q),
442 .ds (),
443
444 // to register interface (read)
445 .qs (ctrl_edn_enable_qs)
446 );
447
448 // F[boot_req_mode]: 7:4
449 prim_subreg #(
450 .DW (4),
451 .SwAccess(prim_subreg_pkg::SwAccessRW),
452 .RESVAL (4'h9),
453 .Mubi (1'b1)
454 ) u_ctrl_boot_req_mode (
455 .clk_i (clk_i),
456 .rst_ni (rst_ni),
457
458 // from register interface
459 .we (ctrl_gated_we),
460 .wd (ctrl_boot_req_mode_wd),
461
462 // from internal hardware
463 .de (1'b0),
464 .d ('0),
465
466 // to internal hardware
467 .qe (),
468 .q (reg2hw.ctrl.boot_req_mode.q),
469 .ds (),
470
471 // to register interface (read)
472 .qs (ctrl_boot_req_mode_qs)
473 );
474
475 // F[auto_req_mode]: 11:8
476 prim_subreg #(
477 .DW (4),
478 .SwAccess(prim_subreg_pkg::SwAccessRW),
479 .RESVAL (4'h9),
480 .Mubi (1'b1)
481 ) u_ctrl_auto_req_mode (
482 .clk_i (clk_i),
483 .rst_ni (rst_ni),
484
485 // from register interface
486 .we (ctrl_gated_we),
487 .wd (ctrl_auto_req_mode_wd),
488
489 // from internal hardware
490 .de (1'b0),
491 .d ('0),
492
493 // to internal hardware
494 .qe (),
495 .q (reg2hw.ctrl.auto_req_mode.q),
496 .ds (),
497
498 // to register interface (read)
499 .qs (ctrl_auto_req_mode_qs)
500 );
501
502 // F[cmd_fifo_rst]: 15:12
503 prim_subreg #(
504 .DW (4),
505 .SwAccess(prim_subreg_pkg::SwAccessRW),
506 .RESVAL (4'h9),
507 .Mubi (1'b1)
508 ) u_ctrl_cmd_fifo_rst (
509 .clk_i (clk_i),
510 .rst_ni (rst_ni),
511
512 // from register interface
513 .we (ctrl_gated_we),
514 .wd (ctrl_cmd_fifo_rst_wd),
515
516 // from internal hardware
517 .de (1'b0),
518 .d ('0),
519
520 // to internal hardware
521 .qe (),
522 .q (reg2hw.ctrl.cmd_fifo_rst.q),
523 .ds (),
524
525 // to register interface (read)
526 .qs (ctrl_cmd_fifo_rst_qs)
527 );
528
529
530 // R[boot_ins_cmd]: V(False)
531 prim_subreg #(
532 .DW (32),
533 .SwAccess(prim_subreg_pkg::SwAccessRW),
534 .RESVAL (32'h901),
535 .Mubi (1'b0)
536 ) u_boot_ins_cmd (
537 .clk_i (clk_i),
538 .rst_ni (rst_ni),
539
540 // from register interface
541 .we (boot_ins_cmd_we),
542 .wd (boot_ins_cmd_wd),
543
544 // from internal hardware
545 .de (1'b0),
546 .d ('0),
547
548 // to internal hardware
549 .qe (),
550 .q (reg2hw.boot_ins_cmd.q),
551 .ds (),
552
553 // to register interface (read)
554 .qs (boot_ins_cmd_qs)
555 );
556
557
558 // R[boot_gen_cmd]: V(False)
559 prim_subreg #(
560 .DW (32),
561 .SwAccess(prim_subreg_pkg::SwAccessRW),
562 .RESVAL (32'hfff003),
563 .Mubi (1'b0)
564 ) u_boot_gen_cmd (
565 .clk_i (clk_i),
566 .rst_ni (rst_ni),
567
568 // from register interface
569 .we (boot_gen_cmd_we),
570 .wd (boot_gen_cmd_wd),
571
572 // from internal hardware
573 .de (1'b0),
574 .d ('0),
575
576 // to internal hardware
577 .qe (),
578 .q (reg2hw.boot_gen_cmd.q),
579 .ds (),
580
581 // to register interface (read)
582 .qs (boot_gen_cmd_qs)
583 );
584
585
586 // R[sw_cmd_req]: V(True)
587 logic sw_cmd_req_qe;
588 logic [0:0] sw_cmd_req_flds_we;
589 1/1 assign sw_cmd_req_qe = &sw_cmd_req_flds_we;
Tests: T1 T2 T3
590 prim_subreg_ext #(
591 .DW (32)
592 ) u_sw_cmd_req (
593 .re (1'b0),
594 .we (sw_cmd_req_we),
595 .wd (sw_cmd_req_wd),
596 .d ('0),
597 .qre (),
598 .qe (sw_cmd_req_flds_we[0]),
599 .q (reg2hw.sw_cmd_req.q),
600 .ds (),
601 .qs ()
602 );
603 1/1 assign reg2hw.sw_cmd_req.qe = sw_cmd_req_qe;
Tests: T1 T2 T3
604
605
606 // R[sw_cmd_sts]: V(False)
607 // F[cmd_reg_rdy]: 0:0
608 prim_subreg #(
609 .DW (1),
610 .SwAccess(prim_subreg_pkg::SwAccessRO),
611 .RESVAL (1'h0),
612 .Mubi (1'b0)
613 ) u_sw_cmd_sts_cmd_reg_rdy (
614 .clk_i (clk_i),
615 .rst_ni (rst_ni),
616
617 // from register interface
618 .we (1'b0),
619 .wd ('0),
620
621 // from internal hardware
622 .de (hw2reg.sw_cmd_sts.cmd_reg_rdy.de),
623 .d (hw2reg.sw_cmd_sts.cmd_reg_rdy.d),
624
625 // to internal hardware
626 .qe (),
627 .q (),
628 .ds (),
629
630 // to register interface (read)
631 .qs (sw_cmd_sts_cmd_reg_rdy_qs)
632 );
633
634 // F[cmd_rdy]: 1:1
635 prim_subreg #(
636 .DW (1),
637 .SwAccess(prim_subreg_pkg::SwAccessRO),
638 .RESVAL (1'h0),
639 .Mubi (1'b0)
640 ) u_sw_cmd_sts_cmd_rdy (
641 .clk_i (clk_i),
642 .rst_ni (rst_ni),
643
644 // from register interface
645 .we (1'b0),
646 .wd ('0),
647
648 // from internal hardware
649 .de (hw2reg.sw_cmd_sts.cmd_rdy.de),
650 .d (hw2reg.sw_cmd_sts.cmd_rdy.d),
651
652 // to internal hardware
653 .qe (),
654 .q (),
655 .ds (),
656
657 // to register interface (read)
658 .qs (sw_cmd_sts_cmd_rdy_qs)
659 );
660
661 // F[cmd_ack]: 2:2
662 prim_subreg #(
663 .DW (1),
664 .SwAccess(prim_subreg_pkg::SwAccessRO),
665 .RESVAL (1'h0),
666 .Mubi (1'b0)
667 ) u_sw_cmd_sts_cmd_ack (
668 .clk_i (clk_i),
669 .rst_ni (rst_ni),
670
671 // from register interface
672 .we (1'b0),
673 .wd ('0),
674
675 // from internal hardware
676 .de (hw2reg.sw_cmd_sts.cmd_ack.de),
677 .d (hw2reg.sw_cmd_sts.cmd_ack.d),
678
679 // to internal hardware
680 .qe (),
681 .q (),
682 .ds (),
683
684 // to register interface (read)
685 .qs (sw_cmd_sts_cmd_ack_qs)
686 );
687
688 // F[cmd_sts]: 5:3
689 prim_subreg #(
690 .DW (3),
691 .SwAccess(prim_subreg_pkg::SwAccessRO),
692 .RESVAL (3'h0),
693 .Mubi (1'b0)
694 ) u_sw_cmd_sts_cmd_sts (
695 .clk_i (clk_i),
696 .rst_ni (rst_ni),
697
698 // from register interface
699 .we (1'b0),
700 .wd ('0),
701
702 // from internal hardware
703 .de (hw2reg.sw_cmd_sts.cmd_sts.de),
704 .d (hw2reg.sw_cmd_sts.cmd_sts.d),
705
706 // to internal hardware
707 .qe (),
708 .q (),
709 .ds (),
710
711 // to register interface (read)
712 .qs (sw_cmd_sts_cmd_sts_qs)
713 );
714
715
716 // R[hw_cmd_sts]: V(False)
717 // F[boot_mode]: 0:0
718 prim_subreg #(
719 .DW (1),
720 .SwAccess(prim_subreg_pkg::SwAccessRO),
721 .RESVAL (1'h0),
722 .Mubi (1'b0)
723 ) u_hw_cmd_sts_boot_mode (
724 .clk_i (clk_i),
725 .rst_ni (rst_ni),
726
727 // from register interface
728 .we (1'b0),
729 .wd ('0),
730
731 // from internal hardware
732 .de (hw2reg.hw_cmd_sts.boot_mode.de),
733 .d (hw2reg.hw_cmd_sts.boot_mode.d),
734
735 // to internal hardware
736 .qe (),
737 .q (),
738 .ds (),
739
740 // to register interface (read)
741 .qs (hw_cmd_sts_boot_mode_qs)
742 );
743
744 // F[auto_mode]: 1:1
745 prim_subreg #(
746 .DW (1),
747 .SwAccess(prim_subreg_pkg::SwAccessRO),
748 .RESVAL (1'h0),
749 .Mubi (1'b0)
750 ) u_hw_cmd_sts_auto_mode (
751 .clk_i (clk_i),
752 .rst_ni (rst_ni),
753
754 // from register interface
755 .we (1'b0),
756 .wd ('0),
757
758 // from internal hardware
759 .de (hw2reg.hw_cmd_sts.auto_mode.de),
760 .d (hw2reg.hw_cmd_sts.auto_mode.d),
761
762 // to internal hardware
763 .qe (),
764 .q (),
765 .ds (),
766
767 // to register interface (read)
768 .qs (hw_cmd_sts_auto_mode_qs)
769 );
770
771 // F[cmd_type]: 5:2
772 prim_subreg #(
773 .DW (4),
774 .SwAccess(prim_subreg_pkg::SwAccessRO),
775 .RESVAL (4'h0),
776 .Mubi (1'b0)
777 ) u_hw_cmd_sts_cmd_type (
778 .clk_i (clk_i),
779 .rst_ni (rst_ni),
780
781 // from register interface
782 .we (1'b0),
783 .wd ('0),
784
785 // from internal hardware
786 .de (hw2reg.hw_cmd_sts.cmd_type.de),
787 .d (hw2reg.hw_cmd_sts.cmd_type.d),
788
789 // to internal hardware
790 .qe (),
791 .q (),
792 .ds (),
793
794 // to register interface (read)
795 .qs (hw_cmd_sts_cmd_type_qs)
796 );
797
798 // F[cmd_ack]: 6:6
799 prim_subreg #(
800 .DW (1),
801 .SwAccess(prim_subreg_pkg::SwAccessRO),
802 .RESVAL (1'h0),
803 .Mubi (1'b0)
804 ) u_hw_cmd_sts_cmd_ack (
805 .clk_i (clk_i),
806 .rst_ni (rst_ni),
807
808 // from register interface
809 .we (1'b0),
810 .wd ('0),
811
812 // from internal hardware
813 .de (hw2reg.hw_cmd_sts.cmd_ack.de),
814 .d (hw2reg.hw_cmd_sts.cmd_ack.d),
815
816 // to internal hardware
817 .qe (),
818 .q (),
819 .ds (),
820
821 // to register interface (read)
822 .qs (hw_cmd_sts_cmd_ack_qs)
823 );
824
825 // F[cmd_sts]: 9:7
826 prim_subreg #(
827 .DW (3),
828 .SwAccess(prim_subreg_pkg::SwAccessRO),
829 .RESVAL (3'h0),
830 .Mubi (1'b0)
831 ) u_hw_cmd_sts_cmd_sts (
832 .clk_i (clk_i),
833 .rst_ni (rst_ni),
834
835 // from register interface
836 .we (1'b0),
837 .wd ('0),
838
839 // from internal hardware
840 .de (hw2reg.hw_cmd_sts.cmd_sts.de),
841 .d (hw2reg.hw_cmd_sts.cmd_sts.d),
842
843 // to internal hardware
844 .qe (),
845 .q (),
846 .ds (),
847
848 // to register interface (read)
849 .qs (hw_cmd_sts_cmd_sts_qs)
850 );
851
852
853 // R[reseed_cmd]: V(True)
854 logic reseed_cmd_qe;
855 logic [0:0] reseed_cmd_flds_we;
856 1/1 assign reseed_cmd_qe = &reseed_cmd_flds_we;
Tests: T5 T10 T19
857 prim_subreg_ext #(
858 .DW (32)
859 ) u_reseed_cmd (
860 .re (1'b0),
861 .we (reseed_cmd_we),
862 .wd (reseed_cmd_wd),
863 .d ('0),
864 .qre (),
865 .qe (reseed_cmd_flds_we[0]),
866 .q (reg2hw.reseed_cmd.q),
867 .ds (),
868 .qs ()
869 );
870 1/1 assign reg2hw.reseed_cmd.qe = reseed_cmd_qe;
Tests: T5 T10 T19
871
872
873 // R[generate_cmd]: V(True)
874 logic generate_cmd_qe;
875 logic [0:0] generate_cmd_flds_we;
876 1/1 assign generate_cmd_qe = &generate_cmd_flds_we;
Tests: T5 T10 T19
877 prim_subreg_ext #(
878 .DW (32)
879 ) u_generate_cmd (
880 .re (1'b0),
881 .we (generate_cmd_we),
882 .wd (generate_cmd_wd),
883 .d ('0),
884 .qre (),
885 .qe (generate_cmd_flds_we[0]),
886 .q (reg2hw.generate_cmd.q),
887 .ds (),
888 .qs ()
889 );
890 1/1 assign reg2hw.generate_cmd.qe = generate_cmd_qe;
Tests: T5 T10 T19
891
892
893 // R[max_num_reqs_between_reseeds]: V(False)
894 logic max_num_reqs_between_reseeds_qe;
895 logic [0:0] max_num_reqs_between_reseeds_flds_we;
896 prim_flop #(
897 .Width(1),
898 .ResetValue(0)
899 ) u_max_num_reqs_between_reseeds0_qe (
900 .clk_i(clk_i),
901 .rst_ni(rst_ni),
902 .d_i(&max_num_reqs_between_reseeds_flds_we),
903 .q_o(max_num_reqs_between_reseeds_qe)
904 );
905 prim_subreg #(
906 .DW (32),
907 .SwAccess(prim_subreg_pkg::SwAccessRW),
908 .RESVAL (32'h0),
909 .Mubi (1'b0)
910 ) u_max_num_reqs_between_reseeds (
911 .clk_i (clk_i),
912 .rst_ni (rst_ni),
913
914 // from register interface
915 .we (max_num_reqs_between_reseeds_we),
916 .wd (max_num_reqs_between_reseeds_wd),
917
918 // from internal hardware
919 .de (1'b0),
920 .d ('0),
921
922 // to internal hardware
923 .qe (max_num_reqs_between_reseeds_flds_we[0]),
924 .q (reg2hw.max_num_reqs_between_reseeds.q),
925 .ds (),
926
927 // to register interface (read)
928 .qs (max_num_reqs_between_reseeds_qs)
929 );
930 1/1 assign reg2hw.max_num_reqs_between_reseeds.qe = max_num_reqs_between_reseeds_qe;
Tests: T1 T2 T3
931
932
933 // R[recov_alert_sts]: V(False)
934 // F[edn_enable_field_alert]: 0:0
935 prim_subreg #(
936 .DW (1),
937 .SwAccess(prim_subreg_pkg::SwAccessW0C),
938 .RESVAL (1'h0),
939 .Mubi (1'b0)
940 ) u_recov_alert_sts_edn_enable_field_alert (
941 .clk_i (clk_i),
942 .rst_ni (rst_ni),
943
944 // from register interface
945 .we (recov_alert_sts_we),
946 .wd (recov_alert_sts_edn_enable_field_alert_wd),
947
948 // from internal hardware
949 .de (hw2reg.recov_alert_sts.edn_enable_field_alert.de),
950 .d (hw2reg.recov_alert_sts.edn_enable_field_alert.d),
951
952 // to internal hardware
953 .qe (),
954 .q (),
955 .ds (),
956
957 // to register interface (read)
958 .qs (recov_alert_sts_edn_enable_field_alert_qs)
959 );
960
961 // F[boot_req_mode_field_alert]: 1:1
962 prim_subreg #(
963 .DW (1),
964 .SwAccess(prim_subreg_pkg::SwAccessW0C),
965 .RESVAL (1'h0),
966 .Mubi (1'b0)
967 ) u_recov_alert_sts_boot_req_mode_field_alert (
968 .clk_i (clk_i),
969 .rst_ni (rst_ni),
970
971 // from register interface
972 .we (recov_alert_sts_we),
973 .wd (recov_alert_sts_boot_req_mode_field_alert_wd),
974
975 // from internal hardware
976 .de (hw2reg.recov_alert_sts.boot_req_mode_field_alert.de),
977 .d (hw2reg.recov_alert_sts.boot_req_mode_field_alert.d),
978
979 // to internal hardware
980 .qe (),
981 .q (),
982 .ds (),
983
984 // to register interface (read)
985 .qs (recov_alert_sts_boot_req_mode_field_alert_qs)
986 );
987
988 // F[auto_req_mode_field_alert]: 2:2
989 prim_subreg #(
990 .DW (1),
991 .SwAccess(prim_subreg_pkg::SwAccessW0C),
992 .RESVAL (1'h0),
993 .Mubi (1'b0)
994 ) u_recov_alert_sts_auto_req_mode_field_alert (
995 .clk_i (clk_i),
996 .rst_ni (rst_ni),
997
998 // from register interface
999 .we (recov_alert_sts_we),
1000 .wd (recov_alert_sts_auto_req_mode_field_alert_wd),
1001
1002 // from internal hardware
1003 .de (hw2reg.recov_alert_sts.auto_req_mode_field_alert.de),
1004 .d (hw2reg.recov_alert_sts.auto_req_mode_field_alert.d),
1005
1006 // to internal hardware
1007 .qe (),
1008 .q (),
1009 .ds (),
1010
1011 // to register interface (read)
1012 .qs (recov_alert_sts_auto_req_mode_field_alert_qs)
1013 );
1014
1015 // F[cmd_fifo_rst_field_alert]: 3:3
1016 prim_subreg #(
1017 .DW (1),
1018 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1019 .RESVAL (1'h0),
1020 .Mubi (1'b0)
1021 ) u_recov_alert_sts_cmd_fifo_rst_field_alert (
1022 .clk_i (clk_i),
1023 .rst_ni (rst_ni),
1024
1025 // from register interface
1026 .we (recov_alert_sts_we),
1027 .wd (recov_alert_sts_cmd_fifo_rst_field_alert_wd),
1028
1029 // from internal hardware
1030 .de (hw2reg.recov_alert_sts.cmd_fifo_rst_field_alert.de),
1031 .d (hw2reg.recov_alert_sts.cmd_fifo_rst_field_alert.d),
1032
1033 // to internal hardware
1034 .qe (),
1035 .q (),
1036 .ds (),
1037
1038 // to register interface (read)
1039 .qs (recov_alert_sts_cmd_fifo_rst_field_alert_qs)
1040 );
1041
1042 // F[edn_bus_cmp_alert]: 12:12
1043 prim_subreg #(
1044 .DW (1),
1045 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1046 .RESVAL (1'h0),
1047 .Mubi (1'b0)
1048 ) u_recov_alert_sts_edn_bus_cmp_alert (
1049 .clk_i (clk_i),
1050 .rst_ni (rst_ni),
1051
1052 // from register interface
1053 .we (recov_alert_sts_we),
1054 .wd (recov_alert_sts_edn_bus_cmp_alert_wd),
1055
1056 // from internal hardware
1057 .de (hw2reg.recov_alert_sts.edn_bus_cmp_alert.de),
1058 .d (hw2reg.recov_alert_sts.edn_bus_cmp_alert.d),
1059
1060 // to internal hardware
1061 .qe (),
1062 .q (),
1063 .ds (),
1064
1065 // to register interface (read)
1066 .qs (recov_alert_sts_edn_bus_cmp_alert_qs)
1067 );
1068
1069 // F[csrng_ack_err]: 13:13
1070 prim_subreg #(
1071 .DW (1),
1072 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1073 .RESVAL (1'h0),
1074 .Mubi (1'b0)
1075 ) u_recov_alert_sts_csrng_ack_err (
1076 .clk_i (clk_i),
1077 .rst_ni (rst_ni),
1078
1079 // from register interface
1080 .we (recov_alert_sts_we),
1081 .wd (recov_alert_sts_csrng_ack_err_wd),
1082
1083 // from internal hardware
1084 .de (hw2reg.recov_alert_sts.csrng_ack_err.de),
1085 .d (hw2reg.recov_alert_sts.csrng_ack_err.d),
1086
1087 // to internal hardware
1088 .qe (),
1089 .q (),
1090 .ds (),
1091
1092 // to register interface (read)
1093 .qs (recov_alert_sts_csrng_ack_err_qs)
1094 );
1095
1096
1097 // R[err_code]: V(False)
1098 // F[sfifo_rescmd_err]: 0:0
1099 prim_subreg #(
1100 .DW (1),
1101 .SwAccess(prim_subreg_pkg::SwAccessRO),
1102 .RESVAL (1'h0),
1103 .Mubi (1'b0)
1104 ) u_err_code_sfifo_rescmd_err (
1105 .clk_i (clk_i),
1106 .rst_ni (rst_ni),
1107
1108 // from register interface
1109 .we (1'b0),
1110 .wd ('0),
1111
1112 // from internal hardware
1113 .de (hw2reg.err_code.sfifo_rescmd_err.de),
1114 .d (hw2reg.err_code.sfifo_rescmd_err.d),
1115
1116 // to internal hardware
1117 .qe (),
1118 .q (),
1119 .ds (),
1120
1121 // to register interface (read)
1122 .qs (err_code_sfifo_rescmd_err_qs)
1123 );
1124
1125 // F[sfifo_gencmd_err]: 1:1
1126 prim_subreg #(
1127 .DW (1),
1128 .SwAccess(prim_subreg_pkg::SwAccessRO),
1129 .RESVAL (1'h0),
1130 .Mubi (1'b0)
1131 ) u_err_code_sfifo_gencmd_err (
1132 .clk_i (clk_i),
1133 .rst_ni (rst_ni),
1134
1135 // from register interface
1136 .we (1'b0),
1137 .wd ('0),
1138
1139 // from internal hardware
1140 .de (hw2reg.err_code.sfifo_gencmd_err.de),
1141 .d (hw2reg.err_code.sfifo_gencmd_err.d),
1142
1143 // to internal hardware
1144 .qe (),
1145 .q (),
1146 .ds (),
1147
1148 // to register interface (read)
1149 .qs (err_code_sfifo_gencmd_err_qs)
1150 );
1151
1152 // F[edn_ack_sm_err]: 20:20
1153 prim_subreg #(
1154 .DW (1),
1155 .SwAccess(prim_subreg_pkg::SwAccessRO),
1156 .RESVAL (1'h0),
1157 .Mubi (1'b0)
1158 ) u_err_code_edn_ack_sm_err (
1159 .clk_i (clk_i),
1160 .rst_ni (rst_ni),
1161
1162 // from register interface
1163 .we (1'b0),
1164 .wd ('0),
1165
1166 // from internal hardware
1167 .de (hw2reg.err_code.edn_ack_sm_err.de),
1168 .d (hw2reg.err_code.edn_ack_sm_err.d),
1169
1170 // to internal hardware
1171 .qe (),
1172 .q (),
1173 .ds (),
1174
1175 // to register interface (read)
1176 .qs (err_code_edn_ack_sm_err_qs)
1177 );
1178
1179 // F[edn_main_sm_err]: 21:21
1180 prim_subreg #(
1181 .DW (1),
1182 .SwAccess(prim_subreg_pkg::SwAccessRO),
1183 .RESVAL (1'h0),
1184 .Mubi (1'b0)
1185 ) u_err_code_edn_main_sm_err (
1186 .clk_i (clk_i),
1187 .rst_ni (rst_ni),
1188
1189 // from register interface
1190 .we (1'b0),
1191 .wd ('0),
1192
1193 // from internal hardware
1194 .de (hw2reg.err_code.edn_main_sm_err.de),
1195 .d (hw2reg.err_code.edn_main_sm_err.d),
1196
1197 // to internal hardware
1198 .qe (),
1199 .q (),
1200 .ds (),
1201
1202 // to register interface (read)
1203 .qs (err_code_edn_main_sm_err_qs)
1204 );
1205
1206 // F[edn_cntr_err]: 22:22
1207 prim_subreg #(
1208 .DW (1),
1209 .SwAccess(prim_subreg_pkg::SwAccessRO),
1210 .RESVAL (1'h0),
1211 .Mubi (1'b0)
1212 ) u_err_code_edn_cntr_err (
1213 .clk_i (clk_i),
1214 .rst_ni (rst_ni),
1215
1216 // from register interface
1217 .we (1'b0),
1218 .wd ('0),
1219
1220 // from internal hardware
1221 .de (hw2reg.err_code.edn_cntr_err.de),
1222 .d (hw2reg.err_code.edn_cntr_err.d),
1223
1224 // to internal hardware
1225 .qe (),
1226 .q (),
1227 .ds (),
1228
1229 // to register interface (read)
1230 .qs (err_code_edn_cntr_err_qs)
1231 );
1232
1233 // F[fifo_write_err]: 28:28
1234 prim_subreg #(
1235 .DW (1),
1236 .SwAccess(prim_subreg_pkg::SwAccessRO),
1237 .RESVAL (1'h0),
1238 .Mubi (1'b0)
1239 ) u_err_code_fifo_write_err (
1240 .clk_i (clk_i),
1241 .rst_ni (rst_ni),
1242
1243 // from register interface
1244 .we (1'b0),
1245 .wd ('0),
1246
1247 // from internal hardware
1248 .de (hw2reg.err_code.fifo_write_err.de),
1249 .d (hw2reg.err_code.fifo_write_err.d),
1250
1251 // to internal hardware
1252 .qe (),
1253 .q (),
1254 .ds (),
1255
1256 // to register interface (read)
1257 .qs (err_code_fifo_write_err_qs)
1258 );
1259
1260 // F[fifo_read_err]: 29:29
1261 prim_subreg #(
1262 .DW (1),
1263 .SwAccess(prim_subreg_pkg::SwAccessRO),
1264 .RESVAL (1'h0),
1265 .Mubi (1'b0)
1266 ) u_err_code_fifo_read_err (
1267 .clk_i (clk_i),
1268 .rst_ni (rst_ni),
1269
1270 // from register interface
1271 .we (1'b0),
1272 .wd ('0),
1273
1274 // from internal hardware
1275 .de (hw2reg.err_code.fifo_read_err.de),
1276 .d (hw2reg.err_code.fifo_read_err.d),
1277
1278 // to internal hardware
1279 .qe (),
1280 .q (),
1281 .ds (),
1282
1283 // to register interface (read)
1284 .qs (err_code_fifo_read_err_qs)
1285 );
1286
1287 // F[fifo_state_err]: 30:30
1288 prim_subreg #(
1289 .DW (1),
1290 .SwAccess(prim_subreg_pkg::SwAccessRO),
1291 .RESVAL (1'h0),
1292 .Mubi (1'b0)
1293 ) u_err_code_fifo_state_err (
1294 .clk_i (clk_i),
1295 .rst_ni (rst_ni),
1296
1297 // from register interface
1298 .we (1'b0),
1299 .wd ('0),
1300
1301 // from internal hardware
1302 .de (hw2reg.err_code.fifo_state_err.de),
1303 .d (hw2reg.err_code.fifo_state_err.d),
1304
1305 // to internal hardware
1306 .qe (),
1307 .q (),
1308 .ds (),
1309
1310 // to register interface (read)
1311 .qs (err_code_fifo_state_err_qs)
1312 );
1313
1314
1315 // R[err_code_test]: V(False)
1316 logic err_code_test_qe;
1317 logic [0:0] err_code_test_flds_we;
1318 prim_flop #(
1319 .Width(1),
1320 .ResetValue(0)
1321 ) u_err_code_test0_qe (
1322 .clk_i(clk_i),
1323 .rst_ni(rst_ni),
1324 .d_i(&err_code_test_flds_we),
1325 .q_o(err_code_test_qe)
1326 );
1327 prim_subreg #(
1328 .DW (5),
1329 .SwAccess(prim_subreg_pkg::SwAccessRW),
1330 .RESVAL (5'h0),
1331 .Mubi (1'b0)
1332 ) u_err_code_test (
1333 .clk_i (clk_i),
1334 .rst_ni (rst_ni),
1335
1336 // from register interface
1337 .we (err_code_test_we),
1338 .wd (err_code_test_wd),
1339
1340 // from internal hardware
1341 .de (1'b0),
1342 .d ('0),
1343
1344 // to internal hardware
1345 .qe (err_code_test_flds_we[0]),
1346 .q (reg2hw.err_code_test.q),
1347 .ds (),
1348
1349 // to register interface (read)
1350 .qs (err_code_test_qs)
1351 );
1352 1/1 assign reg2hw.err_code_test.qe = err_code_test_qe;
Tests: T1 T2 T3
1353
1354
1355 // R[main_sm_state]: V(False)
1356 prim_subreg #(
1357 .DW (9),
1358 .SwAccess(prim_subreg_pkg::SwAccessRO),
1359 .RESVAL (9'hc1),
1360 .Mubi (1'b0)
1361 ) u_main_sm_state (
1362 .clk_i (clk_i),
1363 .rst_ni (rst_ni),
1364
1365 // from register interface
1366 .we (1'b0),
1367 .wd ('0),
1368
1369 // from internal hardware
1370 .de (hw2reg.main_sm_state.de),
1371 .d (hw2reg.main_sm_state.d),
1372
1373 // to internal hardware
1374 .qe (),
1375 .q (),
1376 .ds (),
1377
1378 // to register interface (read)
1379 .qs (main_sm_state_qs)
1380 );
1381
1382
1383
1384 logic [17:0] addr_hit;
1385 always_comb begin
1386 1/1 addr_hit = '0;
Tests: T1 T2 T3
1387 1/1 addr_hit[ 0] = (reg_addr == EDN_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1388 1/1 addr_hit[ 1] = (reg_addr == EDN_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
1389 1/1 addr_hit[ 2] = (reg_addr == EDN_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1390 1/1 addr_hit[ 3] = (reg_addr == EDN_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1391 1/1 addr_hit[ 4] = (reg_addr == EDN_REGWEN_OFFSET);
Tests: T1 T2 T3
1392 1/1 addr_hit[ 5] = (reg_addr == EDN_CTRL_OFFSET);
Tests: T1 T2 T3
1393 1/1 addr_hit[ 6] = (reg_addr == EDN_BOOT_INS_CMD_OFFSET);
Tests: T1 T2 T3
1394 1/1 addr_hit[ 7] = (reg_addr == EDN_BOOT_GEN_CMD_OFFSET);
Tests: T1 T2 T3
1395 1/1 addr_hit[ 8] = (reg_addr == EDN_SW_CMD_REQ_OFFSET);
Tests: T1 T2 T3
1396 1/1 addr_hit[ 9] = (reg_addr == EDN_SW_CMD_STS_OFFSET);
Tests: T1 T2 T3
1397 1/1 addr_hit[10] = (reg_addr == EDN_HW_CMD_STS_OFFSET);
Tests: T1 T2 T3
1398 1/1 addr_hit[11] = (reg_addr == EDN_RESEED_CMD_OFFSET);
Tests: T1 T2 T3
1399 1/1 addr_hit[12] = (reg_addr == EDN_GENERATE_CMD_OFFSET);
Tests: T1 T2 T3
1400 1/1 addr_hit[13] = (reg_addr == EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET);
Tests: T1 T2 T3
1401 1/1 addr_hit[14] = (reg_addr == EDN_RECOV_ALERT_STS_OFFSET);
Tests: T1 T2 T3
1402 1/1 addr_hit[15] = (reg_addr == EDN_ERR_CODE_OFFSET);
Tests: T1 T2 T3
1403 1/1 addr_hit[16] = (reg_addr == EDN_ERR_CODE_TEST_OFFSET);
Tests: T1 T2 T3
1404 1/1 addr_hit[17] = (reg_addr == EDN_MAIN_SM_STATE_OFFSET);
Tests: T1 T2 T3
1405 end
1406
1407 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1408
1409 // Check sub-word write is permitted
1410 always_comb begin
1411 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1412 ((addr_hit[ 0] & (|(EDN_PERMIT[ 0] & ~reg_be))) |
1413 (addr_hit[ 1] & (|(EDN_PERMIT[ 1] & ~reg_be))) |
1414 (addr_hit[ 2] & (|(EDN_PERMIT[ 2] & ~reg_be))) |
1415 (addr_hit[ 3] & (|(EDN_PERMIT[ 3] & ~reg_be))) |
1416 (addr_hit[ 4] & (|(EDN_PERMIT[ 4] & ~reg_be))) |
1417 (addr_hit[ 5] & (|(EDN_PERMIT[ 5] & ~reg_be))) |
1418 (addr_hit[ 6] & (|(EDN_PERMIT[ 6] & ~reg_be))) |
1419 (addr_hit[ 7] & (|(EDN_PERMIT[ 7] & ~reg_be))) |
1420 (addr_hit[ 8] & (|(EDN_PERMIT[ 8] & ~reg_be))) |
1421 (addr_hit[ 9] & (|(EDN_PERMIT[ 9] & ~reg_be))) |
1422 (addr_hit[10] & (|(EDN_PERMIT[10] & ~reg_be))) |
1423 (addr_hit[11] & (|(EDN_PERMIT[11] & ~reg_be))) |
1424 (addr_hit[12] & (|(EDN_PERMIT[12] & ~reg_be))) |
1425 (addr_hit[13] & (|(EDN_PERMIT[13] & ~reg_be))) |
1426 (addr_hit[14] & (|(EDN_PERMIT[14] & ~reg_be))) |
1427 (addr_hit[15] & (|(EDN_PERMIT[15] & ~reg_be))) |
1428 (addr_hit[16] & (|(EDN_PERMIT[16] & ~reg_be))) |
1429 (addr_hit[17] & (|(EDN_PERMIT[17] & ~reg_be)))));
1430 end
1431
1432 // Generate write-enables
1433 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1434
1435 1/1 assign intr_state_edn_cmd_req_done_wd = reg_wdata[0];
Tests: T1 T2 T3
1436
1437 1/1 assign intr_state_edn_fatal_err_wd = reg_wdata[1];
Tests: T1 T2 T3
1438 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1439
1440 1/1 assign intr_enable_edn_cmd_req_done_wd = reg_wdata[0];
Tests: T1 T2 T3
1441
1442 1/1 assign intr_enable_edn_fatal_err_wd = reg_wdata[1];
Tests: T1 T2 T3
1443 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1444
1445 1/1 assign intr_test_edn_cmd_req_done_wd = reg_wdata[0];
Tests: T1 T2 T3
1446
1447 1/1 assign intr_test_edn_fatal_err_wd = reg_wdata[1];
Tests: T1 T2 T3
1448 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1449
1450 1/1 assign alert_test_recov_alert_wd = reg_wdata[0];
Tests: T1 T2 T3
1451
1452 1/1 assign alert_test_fatal_alert_wd = reg_wdata[1];
Tests: T1 T2 T3
1453 1/1 assign regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1454
1455 1/1 assign regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1456 1/1 assign ctrl_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1457
1458 1/1 assign ctrl_edn_enable_wd = reg_wdata[3:0];
Tests: T1 T2 T3
1459
1460 1/1 assign ctrl_boot_req_mode_wd = reg_wdata[7:4];
Tests: T1 T2 T3
1461
1462 1/1 assign ctrl_auto_req_mode_wd = reg_wdata[11:8];
Tests: T1 T2 T3
1463
1464 1/1 assign ctrl_cmd_fifo_rst_wd = reg_wdata[15:12];
Tests: T1 T2 T3
1465 1/1 assign boot_ins_cmd_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1466
1467 1/1 assign boot_ins_cmd_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1468 1/1 assign boot_gen_cmd_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1469
1470 1/1 assign boot_gen_cmd_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1471 1/1 assign sw_cmd_req_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1472
1473 1/1 assign sw_cmd_req_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1474 1/1 assign reseed_cmd_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1475
1476 1/1 assign reseed_cmd_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1477 1/1 assign generate_cmd_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1478
1479 1/1 assign generate_cmd_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1480 1/1 assign max_num_reqs_between_reseeds_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
1481
1482 1/1 assign max_num_reqs_between_reseeds_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1483 1/1 assign recov_alert_sts_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
1484
1485 1/1 assign recov_alert_sts_edn_enable_field_alert_wd = reg_wdata[0];
Tests: T1 T2 T3
1486
1487 1/1 assign recov_alert_sts_boot_req_mode_field_alert_wd = reg_wdata[1];
Tests: T1 T2 T3
1488
1489 1/1 assign recov_alert_sts_auto_req_mode_field_alert_wd = reg_wdata[2];
Tests: T1 T2 T3
1490
1491 1/1 assign recov_alert_sts_cmd_fifo_rst_field_alert_wd = reg_wdata[3];
Tests: T1 T2 T3
1492
1493 1/1 assign recov_alert_sts_edn_bus_cmp_alert_wd = reg_wdata[12];
Tests: T1 T2 T3
1494
1495 1/1 assign recov_alert_sts_csrng_ack_err_wd = reg_wdata[13];
Tests: T1 T2 T3
1496 1/1 assign err_code_test_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
1497
1498 1/1 assign err_code_test_wd = reg_wdata[4:0];
Tests: T1 T2 T3
1499
1500 // Assign write-enables to checker logic vector.
1501 always_comb begin
1502 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1503 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
1504 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
1505 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
1506 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
1507 1/1 reg_we_check[4] = regwen_we;
Tests: T1 T2 T3
1508 1/1 reg_we_check[5] = ctrl_gated_we;
Tests: T1 T2 T3
1509 1/1 reg_we_check[6] = boot_ins_cmd_we;
Tests: T1 T2 T3
1510 1/1 reg_we_check[7] = boot_gen_cmd_we;
Tests: T1 T2 T3
1511 1/1 reg_we_check[8] = sw_cmd_req_we;
Tests: T1 T2 T3
1512 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T2 T3
1513 1/1 reg_we_check[10] = 1'b0;
Tests: T1 T2 T3
1514 1/1 reg_we_check[11] = reseed_cmd_we;
Tests: T1 T2 T3
1515 1/1 reg_we_check[12] = generate_cmd_we;
Tests: T1 T2 T3
1516 1/1 reg_we_check[13] = max_num_reqs_between_reseeds_we;
Tests: T1 T2 T3
1517 1/1 reg_we_check[14] = recov_alert_sts_we;
Tests: T1 T2 T3
1518 1/1 reg_we_check[15] = 1'b0;
Tests: T1 T2 T3
1519 1/1 reg_we_check[16] = err_code_test_we;
Tests: T1 T2 T3
1520 1/1 reg_we_check[17] = 1'b0;
Tests: T1 T2 T3
1521 end
1522
1523 // Read data return
1524 always_comb begin
1525 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1526 1/1 unique case (1'b1)
Tests: T1 T2 T3
1527 addr_hit[0]: begin
1528 1/1 reg_rdata_next[0] = intr_state_edn_cmd_req_done_qs;
Tests: T1 T2 T3
1529 1/1 reg_rdata_next[1] = intr_state_edn_fatal_err_qs;
Tests: T1 T2 T3
1530 end
1531
1532 addr_hit[1]: begin
1533 1/1 reg_rdata_next[0] = intr_enable_edn_cmd_req_done_qs;
Tests: T1 T2 T3
1534 1/1 reg_rdata_next[1] = intr_enable_edn_fatal_err_qs;
Tests: T1 T2 T3
1535 end
1536
1537 addr_hit[2]: begin
1538 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1539 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1540 end
1541
1542 addr_hit[3]: begin
1543 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1544 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1545 end
1546
1547 addr_hit[4]: begin
1548 1/1 reg_rdata_next[0] = regwen_qs;
Tests: T1 T2 T3
1549 end
1550
1551 addr_hit[5]: begin
1552 1/1 reg_rdata_next[3:0] = ctrl_edn_enable_qs;
Tests: T1 T2 T3
1553 1/1 reg_rdata_next[7:4] = ctrl_boot_req_mode_qs;
Tests: T1 T2 T3
1554 1/1 reg_rdata_next[11:8] = ctrl_auto_req_mode_qs;
Tests: T1 T2 T3
1555 1/1 reg_rdata_next[15:12] = ctrl_cmd_fifo_rst_qs;
Tests: T1 T2 T3
1556 end
1557
1558 addr_hit[6]: begin
1559 1/1 reg_rdata_next[31:0] = boot_ins_cmd_qs;
Tests: T1 T2 T3
1560 end
1561
1562 addr_hit[7]: begin
1563 1/1 reg_rdata_next[31:0] = boot_gen_cmd_qs;
Tests: T1 T2 T3
1564 end
1565
1566 addr_hit[8]: begin
1567 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
1568 end
1569
1570 addr_hit[9]: begin
1571 1/1 reg_rdata_next[0] = sw_cmd_sts_cmd_reg_rdy_qs;
Tests: T1 T2 T3
1572 1/1 reg_rdata_next[1] = sw_cmd_sts_cmd_rdy_qs;
Tests: T1 T2 T3
1573 1/1 reg_rdata_next[2] = sw_cmd_sts_cmd_ack_qs;
Tests: T1 T2 T3
1574 1/1 reg_rdata_next[5:3] = sw_cmd_sts_cmd_sts_qs;
Tests: T1 T2 T3
1575 end
1576
1577 addr_hit[10]: begin
1578 1/1 reg_rdata_next[0] = hw_cmd_sts_boot_mode_qs;
Tests: T1 T2 T3
1579 1/1 reg_rdata_next[1] = hw_cmd_sts_auto_mode_qs;
Tests: T1 T2 T3
1580 1/1 reg_rdata_next[5:2] = hw_cmd_sts_cmd_type_qs;
Tests: T1 T2 T3
1581 1/1 reg_rdata_next[6] = hw_cmd_sts_cmd_ack_qs;
Tests: T1 T2 T3
1582 1/1 reg_rdata_next[9:7] = hw_cmd_sts_cmd_sts_qs;
Tests: T1 T2 T3
1583 end
1584
1585 addr_hit[11]: begin
1586 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
1587 end
1588
1589 addr_hit[12]: begin
1590 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
1591 end
1592
1593 addr_hit[13]: begin
1594 1/1 reg_rdata_next[31:0] = max_num_reqs_between_reseeds_qs;
Tests: T1 T2 T3
1595 end
1596
1597 addr_hit[14]: begin
1598 1/1 reg_rdata_next[0] = recov_alert_sts_edn_enable_field_alert_qs;
Tests: T1 T2 T3
1599 1/1 reg_rdata_next[1] = recov_alert_sts_boot_req_mode_field_alert_qs;
Tests: T1 T2 T3
1600 1/1 reg_rdata_next[2] = recov_alert_sts_auto_req_mode_field_alert_qs;
Tests: T1 T2 T3
1601 1/1 reg_rdata_next[3] = recov_alert_sts_cmd_fifo_rst_field_alert_qs;
Tests: T1 T2 T3
1602 1/1 reg_rdata_next[12] = recov_alert_sts_edn_bus_cmp_alert_qs;
Tests: T1 T2 T3
1603 1/1 reg_rdata_next[13] = recov_alert_sts_csrng_ack_err_qs;
Tests: T1 T2 T3
1604 end
1605
1606 addr_hit[15]: begin
1607 1/1 reg_rdata_next[0] = err_code_sfifo_rescmd_err_qs;
Tests: T1 T2 T3
1608 1/1 reg_rdata_next[1] = err_code_sfifo_gencmd_err_qs;
Tests: T1 T2 T3
1609 1/1 reg_rdata_next[20] = err_code_edn_ack_sm_err_qs;
Tests: T1 T2 T3
1610 1/1 reg_rdata_next[21] = err_code_edn_main_sm_err_qs;
Tests: T1 T2 T3
1611 1/1 reg_rdata_next[22] = err_code_edn_cntr_err_qs;
Tests: T1 T2 T3
1612 1/1 reg_rdata_next[28] = err_code_fifo_write_err_qs;
Tests: T1 T2 T3
1613 1/1 reg_rdata_next[29] = err_code_fifo_read_err_qs;
Tests: T1 T2 T3
1614 1/1 reg_rdata_next[30] = err_code_fifo_state_err_qs;
Tests: T1 T2 T3
1615 end
1616
1617 addr_hit[16]: begin
1618 1/1 reg_rdata_next[4:0] = err_code_test_qs;
Tests: T1 T2 T3
1619 end
1620
1621 addr_hit[17]: begin
1622 1/1 reg_rdata_next[8:0] = main_sm_state_qs;
Tests: T1 T2 T3
1623 end
1624
1625 default: begin
1626 reg_rdata_next = '1;
1627 end
1628 endcase
1629 end
1630
1631 // shadow busy
1632 logic shadow_busy;
1633 assign shadow_busy = 1'b0;
1634
1635 // register busy
1636 unreachable assign reg_busy = shadow_busy;
1637
1638 // Unused signal tieoff
1639
1640 // wdata / byte enable are not always fully used
1641 // add a blanket unused statement to handle lint waivers
1642 logic unused_wdata;
1643 logic unused_be;
1644 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1645 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
edn_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 190 | 190 | 100.00 |
| Logical | 190 | 190 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 70
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T17,T18,T20 |
| 1 | 0 | Covered | T310,T311,T312 |
LINE 77
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T17,T18,T20 |
| 0 | 1 | 0 | Covered | T310,T311,T312 |
| 1 | 0 | 0 | Covered | T17,T18,T20 |
LINE 119
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T310,T311,T312 |
| 0 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 0 | 0 | Covered | T38,T39,T40 |
LINE 420
EXPRESSION (ctrl_we & regwen_qs)
---1--- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1387
EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_STATE_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1388
EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_ENABLE_OFFSET)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 1389
EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_TEST_OFFSET)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T6,T29 |
LINE 1390
EXPRESSION (reg_addr == edn_reg_pkg::EDN_ALERT_TEST_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T26 |
LINE 1391
EXPRESSION (reg_addr == edn_reg_pkg::EDN_REGWEN_OFFSET)
----------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1392
EXPRESSION (reg_addr == edn_reg_pkg::EDN_CTRL_OFFSET)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1393
EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_INS_CMD_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 1394
EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_GEN_CMD_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T24 |
LINE 1395
EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_REQ_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1396
EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_STS_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1397
EXPRESSION (reg_addr == edn_reg_pkg::EDN_HW_CMD_STS_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T25,T37 |
LINE 1398
EXPRESSION (reg_addr == edn_reg_pkg::EDN_RESEED_CMD_OFFSET)
------------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T5 |
LINE 1399
EXPRESSION (reg_addr == edn_reg_pkg::EDN_GENERATE_CMD_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T10 |
LINE 1400
EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T10 |
LINE 1401
EXPRESSION (reg_addr == edn_reg_pkg::EDN_RECOV_ALERT_STS_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T25,T19 |
LINE 1402
EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_OFFSET)
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T37 |
LINE 1403
EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_TEST_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T25 |
LINE 1404
EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAIN_SM_STATE_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T25 |
LINE 1407
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1407
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1411
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 1411
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b0011 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T3,T4,T29 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T3,T4,T11 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T3,T5,T37 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T3,T25,T19 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T3,T4,T29 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T37,T29 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T37 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T25,T37,T19 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T29 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T37,T29 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T29 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T4,T37 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T37,T29 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T11,T65 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T6,T11,T64 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T37,T6 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 1411
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1411
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T4,T37,T6 |
LINE 1411
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T6,T29 |
| 1 | 1 | Covered | T6,T11,T64 |
LINE 1411
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T26 |
| 1 | 1 | Covered | T3,T11,T65 |
LINE 1411
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T37,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T37 |
LINE 1411
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T24,T28 |
| 1 | 1 | Covered | T3,T4,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T24,T25 |
| 1 | 1 | Covered | T3,T37,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T4,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1411
SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T25,T29 |
| 1 | 1 | Covered | T25,T37,T19 |
LINE 1411
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T10,T19 |
| 1 | 1 | Covered | T3,T4,T37 |
LINE 1411
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T10,T19 |
| 1 | 1 | Covered | T3,T37,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T29,T11 |
| 1 | 1 | Covered | T3,T4,T29 |
LINE 1411
SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T19,T11 |
| 1 | 1 | Covered | T3,T25,T19 |
LINE 1411
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T32,T70 |
| 1 | 1 | Covered | T3,T5,T37 |
LINE 1411
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T25,T27 |
| 1 | 1 | Covered | T3,T4,T11 |
LINE 1411
SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T25 |
| 1 | 1 | Covered | T3,T4,T29 |
LINE 1433
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1438
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 1443
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T6,T29 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T6,T42,T56 |
LINE 1448
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T26 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T26,T64,T65 |
LINE 1453
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 1456
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1465
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T5,T24,T28 |
LINE 1468
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T5,T24 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T5,T24,T25 |
LINE 1471
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1474
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T5,T10,T19 |
LINE 1477
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T5,T10 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T5,T10,T19 |
LINE 1480
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T10 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 1483
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T25,T19 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T25,T19,T12 |
LINE 1496
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T4,T25 |
| 1 | 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | 1 | Covered | T3,T25,T27 |
Branch Coverage for Module :
edn_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
24 |
100.00 |
| TERNARY |
1407 |
2 |
2 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| CASE |
1526 |
19 |
19 |
100.00 |
1407 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
68 if (!rst_ni) begin
-1-
69 err_q <= '0;
==>
70 end else if (intg_err || reg_we_err) begin
-2-
71 err_q <= 1'b1;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T17,T18,T20 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1526 unique case (1'b1)
-1-
1527 addr_hit[0]: begin
1528 reg_rdata_next[0] = intr_state_edn_cmd_req_done_qs;
==>
1529 reg_rdata_next[1] = intr_state_edn_fatal_err_qs;
1530 end
1531
1532 addr_hit[1]: begin
1533 reg_rdata_next[0] = intr_enable_edn_cmd_req_done_qs;
==>
1534 reg_rdata_next[1] = intr_enable_edn_fatal_err_qs;
1535 end
1536
1537 addr_hit[2]: begin
1538 reg_rdata_next[0] = '0;
==>
1539 reg_rdata_next[1] = '0;
1540 end
1541
1542 addr_hit[3]: begin
1543 reg_rdata_next[0] = '0;
==>
1544 reg_rdata_next[1] = '0;
1545 end
1546
1547 addr_hit[4]: begin
1548 reg_rdata_next[0] = regwen_qs;
==>
1549 end
1550
1551 addr_hit[5]: begin
1552 reg_rdata_next[3:0] = ctrl_edn_enable_qs;
==>
1553 reg_rdata_next[7:4] = ctrl_boot_req_mode_qs;
1554 reg_rdata_next[11:8] = ctrl_auto_req_mode_qs;
1555 reg_rdata_next[15:12] = ctrl_cmd_fifo_rst_qs;
1556 end
1557
1558 addr_hit[6]: begin
1559 reg_rdata_next[31:0] = boot_ins_cmd_qs;
==>
1560 end
1561
1562 addr_hit[7]: begin
1563 reg_rdata_next[31:0] = boot_gen_cmd_qs;
==>
1564 end
1565
1566 addr_hit[8]: begin
1567 reg_rdata_next[31:0] = '0;
==>
1568 end
1569
1570 addr_hit[9]: begin
1571 reg_rdata_next[0] = sw_cmd_sts_cmd_reg_rdy_qs;
==>
1572 reg_rdata_next[1] = sw_cmd_sts_cmd_rdy_qs;
1573 reg_rdata_next[2] = sw_cmd_sts_cmd_ack_qs;
1574 reg_rdata_next[5:3] = sw_cmd_sts_cmd_sts_qs;
1575 end
1576
1577 addr_hit[10]: begin
1578 reg_rdata_next[0] = hw_cmd_sts_boot_mode_qs;
==>
1579 reg_rdata_next[1] = hw_cmd_sts_auto_mode_qs;
1580 reg_rdata_next[5:2] = hw_cmd_sts_cmd_type_qs;
1581 reg_rdata_next[6] = hw_cmd_sts_cmd_ack_qs;
1582 reg_rdata_next[9:7] = hw_cmd_sts_cmd_sts_qs;
1583 end
1584
1585 addr_hit[11]: begin
1586 reg_rdata_next[31:0] = '0;
==>
1587 end
1588
1589 addr_hit[12]: begin
1590 reg_rdata_next[31:0] = '0;
==>
1591 end
1592
1593 addr_hit[13]: begin
1594 reg_rdata_next[31:0] = max_num_reqs_between_reseeds_qs;
==>
1595 end
1596
1597 addr_hit[14]: begin
1598 reg_rdata_next[0] = recov_alert_sts_edn_enable_field_alert_qs;
==>
1599 reg_rdata_next[1] = recov_alert_sts_boot_req_mode_field_alert_qs;
1600 reg_rdata_next[2] = recov_alert_sts_auto_req_mode_field_alert_qs;
1601 reg_rdata_next[3] = recov_alert_sts_cmd_fifo_rst_field_alert_qs;
1602 reg_rdata_next[12] = recov_alert_sts_edn_bus_cmp_alert_qs;
1603 reg_rdata_next[13] = recov_alert_sts_csrng_ack_err_qs;
1604 end
1605
1606 addr_hit[15]: begin
1607 reg_rdata_next[0] = err_code_sfifo_rescmd_err_qs;
==>
1608 reg_rdata_next[1] = err_code_sfifo_gencmd_err_qs;
1609 reg_rdata_next[20] = err_code_edn_ack_sm_err_qs;
1610 reg_rdata_next[21] = err_code_edn_main_sm_err_qs;
1611 reg_rdata_next[22] = err_code_edn_cntr_err_qs;
1612 reg_rdata_next[28] = err_code_fifo_write_err_qs;
1613 reg_rdata_next[29] = err_code_fifo_read_err_qs;
1614 reg_rdata_next[30] = err_code_fifo_state_err_qs;
1615 end
1616
1617 addr_hit[16]: begin
1618 reg_rdata_next[4:0] = err_code_test_qs;
==>
1619 end
1620
1621 addr_hit[17]: begin
1622 reg_rdata_next[8:0] = main_sm_state_qs;
==>
1623 end
1624
1625 default: begin
1626 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| addr_hit[14] |
Covered |
T1,T2,T3 |
| addr_hit[15] |
Covered |
T1,T2,T3 |
| addr_hit[16] |
Covered |
T1,T2,T3 |
| addr_hit[17] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
edn_reg_top
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12359530 |
238838 |
0 |
0 |
| T1 |
1479 |
32 |
0 |
0 |
| T2 |
904 |
55 |
0 |
0 |
| T3 |
3835 |
89 |
0 |
0 |
| T4 |
889 |
31 |
0 |
0 |
| T5 |
1783 |
18 |
0 |
0 |
| T10 |
2747 |
121 |
0 |
0 |
| T24 |
882 |
5 |
0 |
0 |
| T25 |
2039 |
51 |
0 |
0 |
| T26 |
1178 |
21 |
0 |
0 |
| T27 |
1382 |
58 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12359530 |
238838 |
0 |
0 |
| T1 |
1479 |
32 |
0 |
0 |
| T2 |
904 |
55 |
0 |
0 |
| T3 |
3835 |
89 |
0 |
0 |
| T4 |
889 |
31 |
0 |
0 |
| T5 |
1783 |
18 |
0 |
0 |
| T10 |
2747 |
121 |
0 |
0 |
| T24 |
882 |
5 |
0 |
0 |
| T25 |
2039 |
51 |
0 |
0 |
| T26 |
1178 |
21 |
0 |
0 |
| T27 |
1382 |
58 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12359530 |
148209 |
0 |
0 |
| T1 |
1479 |
23 |
0 |
0 |
| T2 |
904 |
46 |
0 |
0 |
| T3 |
3835 |
55 |
0 |
0 |
| T4 |
889 |
17 |
0 |
0 |
| T5 |
1783 |
5 |
0 |
0 |
| T10 |
2747 |
47 |
0 |
0 |
| T24 |
882 |
1 |
0 |
0 |
| T25 |
2039 |
27 |
0 |
0 |
| T26 |
1178 |
1 |
0 |
0 |
| T27 |
1382 |
48 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12359530 |
90629 |
0 |
0 |
| T1 |
1479 |
9 |
0 |
0 |
| T2 |
904 |
9 |
0 |
0 |
| T3 |
3835 |
34 |
0 |
0 |
| T4 |
889 |
14 |
0 |
0 |
| T5 |
1783 |
13 |
0 |
0 |
| T10 |
2747 |
74 |
0 |
0 |
| T24 |
882 |
4 |
0 |
0 |
| T25 |
2039 |
24 |
0 |
0 |
| T26 |
1178 |
20 |
0 |
0 |
| T27 |
1382 |
10 |
0 |
0 |