Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.98	98.23	93.85	97.02	90.70	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	93.91	99.92	92.58	82.54	90.70	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T22,T14,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T3,T4,T28

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T22	Yes	T1,T4,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T21,T22,T15	Yes	T21,T22,T15	INPUT
edn_i[2].edn_req	Yes	Yes	T15,T26,T38	Yes	T15,T26,T38	INPUT
edn_i[3].edn_req	Yes	Yes	T22,T15,T39	Yes	T22,T15,T39	INPUT
edn_i[4].edn_req	Yes	Yes	T14,T15,T40	Yes	T14,T15,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T41,T15	Yes	T9,T41,T15	INPUT
edn_i[6].edn_req	Yes	Yes	T15,T16,T42	Yes	T15,T16,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T20	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T20,T5,T28	Yes	T20,T5,T43	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T21,T22,T27	Yes	T21,T22,T27	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T27,T18,T44	Yes	T27,T18,T19	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T21,T22,T27	Yes	T21,T22,T27	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T26,T38,T45	Yes	T26,T38,T45	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T26,T38,T46	Yes	T26,T38,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T26,T38,T45	Yes	T26,T38,T45	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T22,T39,T47	Yes	T22,T39,T18	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T22,T48,T44	Yes	T22,T47,T48	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T22,T39,T18	Yes	T22,T39,T18	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T14,T40,T49	Yes	T14,T40,T50	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T40,T51,T52	Yes	T14,T40,T50	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T14,T40,T50	Yes	T14,T40,T50	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T18,T53	Yes	T9,T41,T18	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T54,T55,T56	Yes	T9,T53,T54	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T41,T18	Yes	T9,T41,T18	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T42,T55,T49	Yes	T42,T55,T49	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T42,T49,T57	Yes	T42,T55,T49	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T42,T55,T49	Yes	T42,T55,T49	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T20,T21	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T20,T18,T19	Yes	T20,T9,T5	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T20,T22,T5	Yes	T20,T10,T39	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T42,T58,T59	Yes	T42,T58,T59	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T22,T23,T14	Yes	T22,T23,T14	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T23	Yes	T3,T4,T23	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T22,T23,T14	Yes	T22,T23,T14	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T23	Yes	T3,T4,T23	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T5,T28	Yes	T3,T5,T28	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	9178401	9000299	0	0
CsrngAppIfOut_A	9178401	9000299	0	0
FpvSecCmCntAlertCheck_A	9178401	109	0	0
FpvSecCmGenCmdFifoRptrCheck_A	9178401	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	9178401	70	0	0
FpvSecCmMainFsmCheck_A	9178401	70	0	0
FpvSecCmRegWeOnehotCheck_A	9178401	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	9178401	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	9178401	70	0	0
IntrEdnCmdReqDoneKnownO_A	9178401	9000299	0	0
TlAReadyKnownO_A	9178401	9000299	0	0
TlDValidKnownO_A	9178401	9000299	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	9178401	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[0].EdnDataStable_A	9178401	16360	0	403
gen_edn_if_asserts[0].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[1].EdnDataStable_A	9178401	8308	0	140
gen_edn_if_asserts[1].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[2].EdnDataStable_A	9178401	4716	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[3].EdnDataStable_A	9178401	3280	0	125
gen_edn_if_asserts[3].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[4].EdnDataStable_A	9178401	1988	0	103
gen_edn_if_asserts[4].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[5].EdnDataStable_A	9178401	4413	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	9178401	157126	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	9178401	540709	0	274
gen_edn_if_asserts[6].EdnDataStable_A	9178401	5458	0	100
gen_edn_if_asserts[6].EdnEndPointOut_A	9178401	9000299	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	9178401	157126	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	109	0	0
T6	2604	1	0	0
T8	0	1	0	0
T14	2232	0	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T59	0	1	0	0
T60	12480	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	70	0	0
T15	25326	10	0	0
T16	0	10	0	0
T17	0	10	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T70	1023	0	0	0
T71	1041	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	16360	0	403
T1	1173	3	0	1
T2	1350	3	0	1
T3	865	1	0	0
T4	1780	0	0	0
T5	7672	6	0	0
T9	1704	0	0	0
T10	0	4	0	0
T20	4568	11	0	1
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	0	3	0	1
T25	0	0	0	1
T28	0	1	0	0
T43	0	3	0	1
T67	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1
T73	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	8308	0	140
T4	1780	0	0	0
T5	7672	0	0	0
T9	1704	0	0	0
T18	0	1059	0	1
T19	0	5	0	0
T21	1126	3	0	1
T22	2116	4	0	1
T23	1233	0	0	0
T24	990	0	0	0
T27	0	1	0	0
T28	1266	0	0	0
T29	0	1	0	0
T43	1566	0	0	0
T44	0	12	0	1
T49	0	3	0	1
T52	0	18	0	1
T73	1672	0	0	0
T76	0	1	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	4716	0	127
T7	661	0	0	0
T18	7188	0	0	0
T19	2736	0	0	0
T26	2177	4	0	0
T38	0	521	0	1
T40	2314	0	0	0
T44	0	3	0	1
T45	0	4	0	0
T46	0	50	0	1
T47	953	0	0	0
T53	2101	0	0	0
T57	0	0	0	1
T61	18743	0	0	0
T74	2232	0	0	0
T78	0	11	0	1
T80	0	4	0	0
T81	0	4	0	0
T82	0	3	0	1
T83	0	3	0	1
T84	3013	0	0	0
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	3280	0	125
T5	7672	0	0	0
T6	2604	0	0	0
T10	1505	0	0	0
T18	0	3	0	1
T22	2116	4	0	0
T23	1233	0	0	0
T24	990	0	0	0
T28	1266	0	0	0
T39	0	4	0	0
T41	899	0	0	0
T43	1566	0	0	0
T44	0	61	0	1
T46	0	0	0	1
T47	0	3	0	1
T48	0	28	0	1
T52	0	24	0	1
T73	1672	0	0	0
T83	0	3	0	1
T88	0	3	0	1
T89	0	4	0	1
T90	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	1988	0	103
T14	2232	4	0	1
T15	25326	0	0	0
T25	801	0	0	0
T27	1277	0	0	0
T39	1278	0	0	0
T40	0	11	0	1
T46	0	0	0	1
T49	0	3	0	1
T50	0	3	0	1
T51	0	4	0	0
T52	0	70	0	1
T60	12480	0	0	0
T66	1093	0	0	0
T67	1072	0	0	0
T68	865	0	0	0
T69	1675	0	0	0
T83	0	3	0	1
T85	0	0	0	1
T91	0	1	0	0
T92	0	4	0	0
T93	0	4	0	0
T94	0	0	0	1
T95	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	4413	0	92
T5	7672	0	0	0
T9	1704	4	0	0
T10	1505	0	0	0
T18	0	3	0	1
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T28	1266	0	0	0
T41	899	3	0	1
T43	1566	0	0	0
T49	0	3	0	1
T52	0	0	0	1
T53	0	4	0	0
T54	0	4	0	0
T55	0	18	0	1
T56	0	3	0	1
T73	1672	0	0	0
T78	0	0	0	1
T96	0	3	0	1
T97	0	1	0	0
T98	0	0	0	1
T99	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	540709	0	274
T1	1173	12	0	0
T2	1350	19	0	0
T3	865	298	0	0
T4	1780	1042	0	0
T5	7672	858	0	0
T9	1704	554	0	2
T10	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T20	4568	27	0	0
T21	1126	102	0	0
T22	2116	316	0	0
T23	1233	1176	0	2
T53	0	0	0	2
T66	0	0	0	2
T69	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	5458	0	100
T11	0	0	0	1
T17	24899	0	0	0
T42	2346	4	0	0
T44	4075	0	0	0
T46	0	3	0	1
T49	0	21	0	1
T52	0	3	0	1
T55	0	3	0	1
T58	1858	0	0	0
T62	50797	0	0	0
T85	0	0	0	1
T91	1962	0	0	0
T100	0	4	0	0
T101	0	3	0	1
T102	0	4	0	0
T103	0	4	0	0
T104	0	3	0	1
T105	1102	0	0	0
T106	846	0	0	0
T107	1687	0	0	0
T108	1524	0	0	0
T109	0	0	0	1
T110	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	9000299	0	0
T1	1173	1087	0	0
T2	1350	1260	0	0
T3	865	688	0	0
T4	1780	1634	0	0
T5	7672	7169	0	0
T9	1704	1627	0	0
T20	4568	4481	0	0
T21	1126	1036	0	0
T22	2116	2018	0	0
T23	1233	1178	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9178401	157126	0	0
T3	865	360	0	0
T4	1780	1072	0	0
T5	7672	0	0	0
T6	0	1180	0	0
T7	0	272	0	0
T9	1704	0	0	0
T15	0	10955	0	0
T20	4568	0	0	0
T21	1126	0	0	0
T22	2116	0	0	0
T23	1233	0	0	0
T24	990	0	0	0
T27	0	23	0	0
T28	0	582	0	0
T43	1566	0	0	0
T68	0	489	0	0
T74	0	1121	0	0
T75	0	282	0	0