Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	9719187	313609	0	0
boot_gen_cmd_rd_A	9719187	2603	0	0
boot_ins_cmd_rd_A	9719187	3216	0	0
ctrl_rd_A	9719187	3126	0	0
err_code_test_rd_A	9719187	3173	0	0
intr_enable_rd_A	9719187	6554	0	0
max_num_reqs_between_reseeds_rd_A	9719187	3922	0	0
regwen_rd_A	9719187	4194	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	313609	0	0
T35	60430	2142	0	0
T36	0	7820	0	0
T37	0	10384	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	133	0	0
T241	0	5838	0	0
T242	0	19542	0	0
T243	0	10869	0	0
T244	0	12291	0	0
T245	0	13372	0	0
T246	0	10488	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	2603	0	0
T35	60430	34	0	0
T36	0	170	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	38	0	0
T241	0	234	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0
T252	0	33	0	0
T253	0	296	0	0
T254	0	296	0	0
T255	0	502	0	0
T256	0	471	0	0
T257	0	321	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	3216	0	0
T35	60430	30	0	0
T36	0	184	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	31	0	0
T241	0	240	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0
T252	0	77	0	0
T253	0	358	0	0
T254	0	322	0	0
T255	0	676	0	0
T256	0	746	0	0
T257	0	328	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	3126	0	0
T29	924	0	0	0
T35	0	46	0	0
T36	0	199	0	0
T49	3037	0	0	0
T55	4466	0	0	0
T63	42843	0	0	0
T81	1947	0	0	0
T100	2485	0	0	0
T115	18639	0	0	0
T122	0	8	0	0
T125	1515	5	0	0
T138	1852	0	0	0
T240	0	23	0	0
T258	0	33	0	0
T259	0	1	0	0
T260	0	1	0	0
T261	0	4	0	0
T262	0	8	0	0
T263	879	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	3173	0	0
T35	60430	67	0	0
T36	0	166	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	35	0	0
T241	0	242	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0
T252	0	67	0	0
T253	0	447	0	0
T254	0	383	0	0
T255	0	645	0	0
T256	0	540	0	0
T257	0	307	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	6554	0	0
T30	806	0	0	0
T35	0	49	0	0
T36	0	364	0	0
T65	791	0	0	0
T92	907	0	0	0
T117	24842	0	0	0
T122	23242	38	0	0
T179	1813	0	0	0
T181	2655	0	0	0
T240	0	68	0	0
T258	0	83	0	0
T260	0	10	0	0
T261	0	88	0	0
T262	0	17	0	0
T264	0	59	0	0
T265	0	28	0	0
T266	2085	0	0	0
T267	1326	0	0	0
T268	1668	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	3922	0	0
T35	60430	43	0	0
T36	0	117	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	31	0	0
T241	0	246	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0
T252	0	70	0	0
T253	0	370	0	0
T254	0	339	0	0
T255	0	537	0	0
T256	0	632	0	0
T257	0	284	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9719187	4194	0	0
T35	60430	68	0	0
T36	0	154	0	0
T52	2970	0	0	0
T76	2607	0	0	0
T88	1144	0	0	0
T102	2176	0	0	0
T240	0	16	0	0
T241	0	258	0	0
T247	1269	0	0	0
T248	23171	0	0	0
T249	1605	0	0	0
T250	7743	0	0	0
T251	1578	0	0	0
T252	0	58	0	0
T253	0	436	0	0
T254	0	380	0	0
T255	0	533	0	0
T256	0	663	0	0
T257	0	324	0	0