Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.38	98.23	93.91	97.02	93.02	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00						100.00
u_edn_core	94.31	99.92	92.66	82.54	93.02	98.83	98.90
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T23,T10,T27

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T18
1	0	Covered	T4,T5,T28

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T23,T6	Yes	T1,T23,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T5,T15,T14	Yes	T5,T15,T14	INPUT
edn_i[2].edn_req	Yes	Yes	T26,T15,T38	Yes	T26,T15,T38	INPUT
edn_i[3].edn_req	Yes	Yes	T9,T15,T16	Yes	T9,T15,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T15,T19,T16	Yes	T15,T19,T16	INPUT
edn_i[5].edn_req	Yes	Yes	T24,T15,T16	Yes	T24,T15,T16	INPUT
edn_i[6].edn_req	Yes	Yes	T26,T15,T27	Yes	T26,T15,T27	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T23	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T6,T11	Yes	T1,T3,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T14,T39,T40	Yes	T14,T39,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T39,T41,T42	Yes	T39,T41,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T14,T39,T40	Yes	T14,T39,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T43,T44,T45	Yes	T38,T43,T44	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T46,T47,T48	Yes	T26,T38,T46	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T26,T38,T46	Yes	T26,T38,T46	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T7,T49,T47	Yes	T9,T7,T44	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T47,T50,T12	Yes	T49,T47,T50	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T9,T44,T49	Yes	T9,T44,T49	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T39,T51,T44	Yes	T19,T39,T51	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T39,T51,T49	Yes	T39,T51,T20	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T19,T39,T51	Yes	T19,T39,T51	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T24,T44,T49	Yes	T24,T43,T52	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T24,T44,T53	Yes	T24,T43,T52	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T24,T43,T52	Yes	T24,T43,T52	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T26,T27,T54	Yes	T26,T27,T54	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T26,T27,T55	Yes	T26,T27,T55	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T26,T27,T54	Yes	T26,T27,T54	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T23	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T24,T26,T11	Yes	T23,T6,T26	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T6,T24,T26	Yes	T23,T26,T14	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T22,T23,T59	Yes	T22,T23,T59	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T22	Yes	T4,T5,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T22,T23,T59	Yes	T22,T23,T59	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T22	Yes	T4,T5,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T60,T61	Yes	T6,T60,T61	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T60	Yes	T4,T6,T60	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	10948233	10763862	0	0
CsrngAppIfOut_A	10948233	10763862	0	0
FpvSecCmCntAlertCheck_A	10948233	122	0	0
FpvSecCmGenCmdFifoRptrCheck_A	10948233	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	10948233	80	0	0
FpvSecCmMainFsmCheck_A	10948233	80	0	0
FpvSecCmRegWeOnehotCheck_A	10948233	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	10948233	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	10948233	80	0	0
IntrEdnCmdReqDoneKnownO_A	10948233	10763862	0	0
TlAReadyKnownO_A	10948233	10763862	0	0
TlDValidKnownO_A	10948233	10763862	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	10948233	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[0].EdnDataStable_A	10948233	69772	0	434
gen_edn_if_asserts[0].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[1].EdnDataStable_A	10948233	5435	0	133
gen_edn_if_asserts[1].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[2].EdnDataStable_A	10948233	5514	0	128
gen_edn_if_asserts[2].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[3].EdnDataStable_A	10948233	2338	0	105
gen_edn_if_asserts[3].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[4].EdnDataStable_A	10948233	4836	0	103
gen_edn_if_asserts[4].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[5].EdnDataStable_A	10948233	3431	0	86
gen_edn_if_asserts[5].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	10948233	165917	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	10948233	566195	0	280
gen_edn_if_asserts[6].EdnDataStable_A	10948233	1878	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	10948233	10763862	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	10948233	165917	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	122	0	0
T7	0	1	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T40	0	1	0	0
T46	915	0	0	0
T62	0	1	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	80	0	0
T11	4152	0	0	0
T14	3457	0	0	0
T15	22637	10	0	0
T16	0	10	0	0
T18	0	20	0	0
T19	2271	0	0	0
T29	1255	0	0	0
T38	1236	0	0	0
T46	915	0	0	0
T63	0	20	0	0
T64	0	20	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	69772	0	434
T1	1112	3	0	1
T2	1001	3	0	1
T3	1400	3	0	1
T4	2011	1	0	0
T5	1303	0	0	0
T6	15518	9	0	1
T9	2762	0	0	0
T10	0	0	0	1
T22	750	0	0	0
T23	1742	8	0	1
T24	1221	0	0	0
T25	0	3	0	1
T26	0	19	0	1
T28	0	1	0	0
T68	0	0	0	1
T71	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	5435	0	133
T11	4152	0	0	0
T14	3457	4	0	0
T19	2271	0	0	0
T27	2501	0	0	0
T29	1255	0	0	0
T39	0	35	0	1
T40	0	1	0	0
T41	0	69	0	1
T42	0	19	0	1
T46	915	0	0	0
T47	0	3	0	1
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0
T72	1876	0	0	0
T74	0	3	0	1
T75	0	1	0	0
T76	0	4	0	0
T77	0	3	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	5514	0	128
T10	1703	0	0	0
T14	3457	0	0	0
T15	22637	0	0	0
T17	1885	0	0	0
T26	4529	3	0	1
T28	1808	0	0	0
T38	1236	3	0	1
T42	0	0	0	1
T43	0	4	0	0
T44	0	6	0	1
T45	0	3	0	1
T46	0	3	0	1
T47	0	52	0	1
T57	0	4	0	1
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0
T82	0	4	0	1
T83	0	5	0	0
T84	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	2338	0	105
T9	2762	3	0	1
T10	1703	0	0	0
T12	0	48	0	1
T15	22637	0	0	0
T17	1885	0	0	0
T25	1633	0	0	0
T26	4529	0	0	0
T28	1808	0	0	0
T44	0	3	0	1
T47	0	34	0	1
T49	0	12	0	1
T50	0	3	0	1
T59	1637	0	0	0
T60	4196	0	0	0
T71	1482	0	0	0
T78	0	9	0	1
T80	0	0	0	1
T85	0	4	0	0
T86	0	1	0	0
T87	0	18	0	1
T88	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	4836	0	103
T12	0	0	0	1
T16	25267	0	0	0
T19	2271	4	0	0
T20	0	4	0	0
T27	2501	0	0	0
T39	1740	36	0	1
T44	0	3	0	1
T46	915	0	0	0
T47	0	44	0	1
T49	0	48	0	1
T51	0	4	0	0
T61	26364	0	0	0
T70	1158	0	0	0
T72	1876	0	0	0
T78	0	0	0	1
T88	0	0	0	1
T89	0	4	0	0
T90	0	4	0	0
T91	0	4	0	1
T92	776	0	0	0
T93	1265	0	0	0
T94	0	0	0	1
T95	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	3431	0	86
T9	2762	0	0	0
T10	1703	0	0	0
T17	1885	0	0	0
T24	1221	4	0	0
T25	1633	0	0	0
T26	4529	0	0	0
T28	1808	0	0	0
T33	0	1	0	0
T43	0	1	0	0
T44	0	41	0	1
T49	0	3	0	1
T52	0	3	0	1
T59	1637	0	0	0
T60	4196	0	0	0
T71	1482	0	0	0
T80	0	0	0	1
T86	0	4	0	0
T87	0	0	0	1
T96	0	4	0	1
T97	0	3	0	1
T98	0	4	0	0
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	566195	0	280
T1	1112	31	0	0
T2	1001	15	0	0
T3	1400	13	0	0
T4	2011	1017	0	0
T5	1303	905	0	0
T6	15518	1296	0	0
T9	2762	187	0	0
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T19	0	0	0	2
T22	750	679	0	2
T23	1742	135	0	0
T24	1221	30	0	0
T43	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T67	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	1878	0	83
T10	1703	0	0	0
T14	3457	0	0	0
T15	22637	0	0	0
T17	1885	0	0	0
T26	4529	18	0	1
T27	0	8	0	1
T28	1808	0	0	0
T38	1236	0	0	0
T49	0	34	0	1
T54	0	4	0	1
T55	0	4	0	0
T57	0	4	0	0
T67	1209	0	0	0
T68	1864	0	0	0
T69	1103	0	0	0
T102	0	1	0	0
T103	0	3	0	1
T104	0	3	0	1
T105	0	1	0	0
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	10763862	0	0
T1	1112	1053	0	0
T2	1001	924	0	0
T3	1400	1329	0	0
T4	2011	1852	0	0
T5	1303	1172	0	0
T6	15518	15020	0	0
T9	2762	2678	0	0
T22	750	681	0	0
T23	1742	1688	0	0
T24	1221	1132	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10948233	165917	0	0
T4	2011	21	0	0
T5	1303	355	0	0
T6	15518	0	0	0
T7	0	614	0	0
T9	2762	0	0	0
T15	0	7774	0	0
T16	0	10684	0	0
T17	0	420	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T28	0	28	0	0
T29	0	18	0	0
T59	1637	0	0	0
T71	1482	0	0	0
T72	0	1112	0	0
T73	0	210	0	0