Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11405037	394694	0	0
boot_gen_cmd_rd_A	11405037	3059	0	0
boot_ins_cmd_rd_A	11405037	3434	0	0
ctrl_rd_A	11405037	3306	0	0
err_code_test_rd_A	11405037	3234	0	0
intr_enable_rd_A	11405037	6593	0	0
max_num_reqs_between_reseeds_rd_A	11405037	4037	0	0
regwen_rd_A	11405037	4370	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	394694	0	0
T35	329857	12075	0	0
T36	0	8674	0	0
T37	0	7058	0	0
T108	2151	0	0	0
T217	0	14560	0	0
T221	1800	0	0	0
T237	0	8265	0	0
T238	0	16054	0	0
T239	0	6209	0	0
T240	0	11389	0	0
T241	0	14942	0	0
T242	0	8493	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	3059	0	0
T35	329857	381	0	0
T36	0	291	0	0
T108	2151	0	0	0
T221	1800	0	0	0
T238	0	475	0	0
T240	0	190	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0
T250	0	409	0	0
T251	0	482	0	0
T252	0	268	0	0
T253	0	76	0	0
T254	0	7	0	0
T255	0	7	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	3434	0	0
T35	329857	429	0	0
T36	0	321	0	0
T108	2151	0	0	0
T221	1800	0	0	0
T238	0	453	0	0
T240	0	194	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0
T250	0	482	0	0
T251	0	599	0	0
T252	0	305	0	0
T253	0	70	0	0
T254	0	25	0	0
T255	0	13	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	3306	0	0
T2	1001	1	0	0
T3	1400	0	0	0
T4	2011	0	0	0
T5	1303	0	0	0
T6	15518	0	0	0
T9	2762	0	0	0
T22	750	0	0	0
T23	1742	0	0	0
T24	1221	0	0	0
T25	0	4	0	0
T35	0	325	0	0
T69	0	3	0	0
T71	1482	0	0	0
T78	0	2	0	0
T94	0	4	0	0
T248	0	5	0	0
T256	0	1	0	0
T257	0	9	0	0
T258	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	3234	0	0
T35	329857	393	0	0
T36	0	325	0	0
T108	2151	0	0	0
T221	1800	0	0	0
T238	0	457	0	0
T240	0	192	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0
T250	0	534	0	0
T251	0	528	0	0
T252	0	260	0	0
T253	0	98	0	0
T254	0	55	0	0
T255	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	6593	0	0
T6	15518	31	0	0
T9	2762	0	0	0
T17	1885	0	0	0
T24	1221	0	0	0
T25	1633	0	0	0
T26	4529	0	0	0
T28	1808	0	0	0
T35	0	598	0	0
T36	0	388	0	0
T59	1637	0	0	0
T60	4196	0	0	0
T71	1482	0	0	0
T115	0	56	0	0
T129	0	38	0	0
T238	0	805	0	0
T240	0	320	0	0
T259	0	27	0	0
T260	0	52	0	0
T261	0	99	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	4037	0	0
T35	329857	364	0	0
T36	0	362	0	0
T108	2151	0	0	0
T221	1800	0	0	0
T238	0	481	0	0
T240	0	199	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0
T250	0	338	0	0
T251	0	535	0	0
T252	0	283	0	0
T253	0	95	0	0
T262	0	25	0	0
T263	0	5	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11405037	4370	0	0
T35	329857	403	0	0
T36	0	299	0	0
T108	2151	0	0	0
T221	1800	0	0	0
T238	0	509	0	0
T240	0	236	0	0
T243	1257	0	0	0
T244	1911	0	0	0
T245	21555	0	0	0
T246	1693	0	0	0
T247	1620	0	0	0
T248	2651	0	0	0
T249	1639	0	0	0
T250	0	551	0	0
T251	0	651	0	0
T252	0	309	0	0
T253	0	68	0	0
T262	0	35	0	0
T263	0	3	0	0