Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.20	98.25	93.91	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.11	99.92	92.66	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T28,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T5,T6,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T5,T30	Yes	T3,T5,T30	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T9,T30	Yes	T3,T9,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T16,T28,T17	Yes	T16,T28,T17	INPUT
edn_i[4].edn_req	Yes	Yes	T6,T16,T17	Yes	T6,T16,T17	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T16,T31	Yes	T3,T16,T31	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T10,T16	Yes	T3,T10,T16	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T24,T30	Yes	T1,T3,T24	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T5,T30	Yes	T3,T5,T30	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T5,T30,T40	Yes	T5,T30,T14	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T5,T30	Yes	T3,T5,T30	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T9,T30	Yes	T3,T9,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T30,T20,T41	Yes	T3,T30,T14	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T9,T30	Yes	T3,T9,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T28,T19,T42	Yes	T28,T19,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T41,T43,T44	Yes	T28,T41,T43	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T28,T19,T42	Yes	T28,T19,T42	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T45,T46,T47	Yes	T45,T48,T46	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T49,T41,T50	Yes	T48,T49,T51	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T45,T48,T46	Yes	T45,T48,T46	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T31,T52	Yes	T3,T31,T52	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T3,T52,T50	Yes	T3,T52,T50	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T31,T52	Yes	T3,T31,T52	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T10,T21	Yes	T3,T10,T21	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T3,T53,T44	Yes	T3,T53,T54	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T10,T21	Yes	T3,T10,T21	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T24,T10	Yes	T3,T10,T30	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T9,T24	Yes	T3,T10,T30	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T28,T29,T55	Yes	T28,T29,T55	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T25,T28	Yes	T9,T25,T28	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T6,T25	Yes	T5,T6,T25	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T25,T28	Yes	T9,T25,T28	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T6,T25	Yes	T5,T6,T25	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	198951858	198785308	0	0
CsrngAppIfOut_A	198951858	198785308	0	0
FpvSecCmCntAlertCheck_A	198951858	101	0	0
FpvSecCmGenCmdFifoRptrCheck_A	198951858	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	198951858	60	0	0
FpvSecCmMainFsmCheck_A	198951858	60	0	0
FpvSecCmRegWeOnehotCheck_A	198951858	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	198951858	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	198951858	60	0	0
IntrEdnCmdReqDoneKnownO_A	198951858	198785308	0	0
TlAReadyKnownO_A	198951858	198785308	0	0
TlDValidKnownO_A	198951858	198785308	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	198951858	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[0].EdnDataStable_A	198951858	23706	0	426
gen_edn_if_asserts[0].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[1].EdnDataStable_A	198951858	5618	0	128
gen_edn_if_asserts[1].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[2].EdnDataStable_A	198951858	5500	0	126
gen_edn_if_asserts[2].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[3].EdnDataStable_A	198951858	4117	0	120
gen_edn_if_asserts[3].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[4].EdnDataStable_A	198951858	2758	0	94
gen_edn_if_asserts[4].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[5].EdnDataStable_A	198951858	3157	0	84
gen_edn_if_asserts[5].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	198951858	139752	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	198951858	555412	0	312
gen_edn_if_asserts[6].EdnDataStable_A	198951858	2943	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	198951858	198785308	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	198951858	139752	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	101	0	0
T7	2615	0	0	0
T8	0	1	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	60	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T16	50309	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T23	0	10	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T56	11358	0	0	0
T58	0	10	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	23706	0	426
T1	1376	3	0	1
T2	1212	3	0	1
T3	2198	29	0	1
T4	5896	3	0	0
T5	696	0	0	0
T6	2497	0	0	0
T9	1767	0	0	0
T10	3087	4	0	0
T24	664	4	0	0
T25	1216	0	0	0
T26	0	3	0	1
T27	0	0	0	1
T30	0	25	0	1
T56	0	13	0	1
T63	0	0	0	1
T65	0	0	0	1
T67	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	5618	0	128
T3	2198	3	0	1
T4	5896	0	0	0
T5	696	1	0	0
T6	2497	0	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T14	0	4	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T28	0	4	0	0
T30	0	36	0	1
T40	0	55	0	1
T50	0	0	0	1
T67	1096	0	0	0
T70	0	1	0	0
T71	0	3	0	1
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	5500	0	126
T3	2198	3	0	1
T4	5896	0	0	0
T5	696	0	0	0
T6	2497	0	0	0
T9	1767	4	0	1
T10	3087	0	0	0
T14	0	1	0	0
T20	0	55	0	1
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	0	45	0	1
T40	0	3	0	1
T41	0	63	0	1
T67	1096	0	0	0
T72	0	3	0	1
T77	0	1	0	0
T78	0	3	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	4117	0	120
T7	2615	0	0	0
T14	2943	0	0	0
T15	7412	0	0	0
T17	24901	0	0	0
T19	0	4	0	0
T27	1272	0	0	0
T28	2962	4	0	1
T41	0	47	0	1
T42	0	4	0	1
T43	0	4	0	0
T44	0	44	0	1
T50	0	3	0	1
T54	0	4	0	0
T57	8231	0	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0
T81	0	3	0	1
T82	0	3	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	2758	0	94
T18	25903	0	0	0
T19	2791	0	0	0
T41	0	56	0	1
T45	1208	3	0	1
T46	0	4	0	0
T47	0	4	0	1
T48	0	3	0	1
T49	0	28	0	1
T50	0	23	0	1
T51	0	4	0	0
T53	0	4	0	1
T66	1743	0	0	0
T69	2166	0	0	0
T70	1361	0	0	0
T74	0	0	0	1
T75	0	0	0	1
T86	0	4	0	1
T87	1474	0	0	0
T88	1294	0	0	0
T89	3993	0	0	0
T90	9893	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	3157	0	84
T3	2198	13	0	1
T4	5896	0	0	0
T5	696	0	0	0
T6	2497	0	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T31	0	1	0	0
T44	0	41	0	1
T50	0	15	0	1
T52	0	4	0	0
T67	1096	0	0	0
T75	0	0	0	1
T79	0	3	0	1
T91	0	4	0	0
T92	0	4	0	0
T93	0	15	0	1
T94	0	1	0	0
T95	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	555412	0	312
T1	1376	12	0	0
T2	1212	18	0	0
T3	2198	56	0	0
T4	5896	1195	0	2
T5	696	214	0	0
T6	2497	1604	0	0
T9	1767	138	0	0
T10	3087	1598	0	2
T14	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T24	664	49	0	0
T25	1216	1123	0	2
T64	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	2943	0	79
T3	2198	47	0	1
T4	5896	0	0	0
T5	696	0	0	0
T6	2497	0	0	0
T9	1767	0	0	0
T10	3087	4	0	0
T21	0	4	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T44	0	21	0	1
T50	0	3	0	1
T53	0	4	0	0
T54	0	1	0	0
T67	1096	0	0	0
T75	0	0	0	1
T84	0	0	0	1
T98	0	0	0	1
T99	0	3	0	1
T100	0	4	0	1
T101	0	4	0	0
T102	0	0	0	1
T103	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	198785308	0	0
T1	1376	1292	0	0
T2	1212	1160	0	0
T3	2198	2114	0	0
T4	5896	5670	0	0
T5	696	551	0	0
T6	2497	2341	0	0
T9	1767	1704	0	0
T10	3087	2994	0	0
T24	664	588	0	0
T25	1216	1125	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198951858	139752	0	0
T5	696	30	0	0
T6	2497	1096	0	0
T7	0	1153	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T16	50309	22544	0	0
T17	0	9985	0	0
T18	0	6859	0	0
T24	664	0	0	0
T25	1216	0	0	0
T26	979	0	0	0
T30	3585	0	0	0
T31	0	1110	0	0
T67	1096	0	0	0
T68	0	590	0	0
T69	0	635	0	0
T70	0	658	0	0