Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	199471557	9320306	0	0
boot_gen_cmd_rd_A	199471557	36036	0	0
boot_ins_cmd_rd_A	199471557	42290	0	0
ctrl_rd_A	199471557	36509	0	0
err_code_test_rd_A	199471557	40837	0	0
intr_enable_rd_A	199471557	41136	0	0
max_num_reqs_between_reseeds_rd_A	199471557	37802	0	0
regwen_rd_A	199471557	42922	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	9320306	0	0
T37	137446	50139	0	0
T38	100013	43207	0	0
T39	0	81140	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	63180	0	0
T235	0	115458	0	0
T236	0	133478	0	0
T237	0	125759	0	0
T238	0	105194	0	0
T239	0	140818	0	0
T240	0	148710	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	36036	0	0
T37	137446	861	0	0
T38	100013	0	0	0
T39	0	2591	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	921	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0
T244	0	1898	0	0
T245	0	2113	0	0
T246	0	2173	0	0
T247	0	7560	0	0
T248	0	1580	0	0
T249	0	5060	0	0
T250	0	3636	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	42290	0	0
T37	137446	984	0	0
T38	100013	0	0	0
T39	0	2838	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	1005	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0
T244	0	2348	0	0
T245	0	2258	0	0
T246	0	2461	0	0
T247	0	9197	0	0
T248	0	1879	0	0
T249	0	5723	0	0
T250	0	4387	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	36509	0	0
T2	1212	5	0	0
T3	2198	0	0	0
T4	5896	0	0	0
T5	696	0	0	0
T6	2497	0	0	0
T9	1767	0	0	0
T10	3087	0	0	0
T24	664	0	0	0
T25	1216	0	0	0
T34	0	2	0	0
T37	0	822	0	0
T56	0	4	0	0
T67	1096	0	0	0
T78	0	9	0	0
T115	0	6	0	0
T122	0	1	0	0
T146	0	3	0	0
T199	0	3	0	0
T251	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	40837	0	0
T37	137446	1002	0	0
T38	100013	0	0	0
T39	0	2653	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	1037	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0
T244	0	2160	0	0
T245	0	2465	0	0
T246	0	2676	0	0
T247	0	8308	0	0
T248	0	1917	0	0
T249	0	5880	0	0
T250	0	4213	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	41136	0	0
T7	2615	0	0	0
T14	2943	0	0	0
T17	24901	0	0	0
T27	1272	0	0	0
T28	2962	0	0	0
T31	2126	0	0	0
T37	0	921	0	0
T39	0	2647	0	0
T56	11358	56	0	0
T63	902	0	0	0
T64	1297	0	0	0
T65	1741	0	0	0
T90	0	39	0	0
T234	0	1130	0	0
T252	0	57	0	0
T253	0	52	0	0
T254	0	91	0	0
T255	0	67	0	0
T256	0	114	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	37802	0	0
T37	137446	662	0	0
T38	100013	0	0	0
T39	0	2512	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	994	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0
T244	0	1863	0	0
T245	0	2112	0	0
T246	0	2369	0	0
T247	0	7626	0	0
T248	0	1677	0	0
T249	0	5165	0	0
T250	0	3950	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199471557	42922	0	0
T37	137446	997	0	0
T38	100013	0	0	0
T39	0	2868	0	0
T74	5701	0	0	0
T102	1925	0	0	0
T158	1776	0	0	0
T216	2302	0	0	0
T229	952	0	0	0
T234	0	1196	0	0
T241	1344	0	0	0
T242	680	0	0	0
T243	737	0	0	0
T244	0	2090	0	0
T245	0	2343	0	0
T246	0	2813	0	0
T247	0	8874	0	0
T248	0	2041	0	0
T249	0	5565	0	0
T250	0	4315	0	0