ENTROPY_SRC Simulation Results

Wednesday November 01 2023 19:03:40 UTC

GitHub Revision: 81a099ffe

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 27873820941847380568675700688072806075234726090008181917214625014019073121880

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 56.915us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 104.291us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 13.000s 81.691us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 1.303ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 533.041us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 13.000s 88.841us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 13.000s 81.691us 20 20 100.00
entropy_src_csr_aliasing 9.000s 533.041us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 56.915us 50 50 100.00
entropy_src_rng 1.767m 10.048ms 300 300 100.00
entropy_src_fw_ov 59.000s 5.135ms 300 300 100.00
V2 firmware_mode entropy_src_fw_ov 59.000s 5.135ms 300 300 100.00
V2 rng_mode entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 3.700m 10.018ms 400 400 100.00
V2 health_checks entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2 conditioning entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2 interrupts entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2 alerts entropy_src_rng 1.767m 10.048ms 300 300 100.00
entropy_src_functional_alerts 5.000s 124.937us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.000s 218.118us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 88.437us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 8.000s 70.591us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 62.241us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 354.791us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 354.791us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 104.291us 5 5 100.00
entropy_src_csr_rw 13.000s 81.691us 20 20 100.00
entropy_src_csr_aliasing 9.000s 533.041us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 173.391us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 104.291us 5 5 100.00
entropy_src_csr_rw 13.000s 81.691us 20 20 100.00
entropy_src_csr_aliasing 9.000s 533.041us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 173.391us 20 20 100.00
V2 TOTAL 2240 2240 100.00
V2S tl_intg_err entropy_src_sec_cm 3.000s 187.991us 5 5 100.00
entropy_src_tl_intg_err 9.000s 392.841us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 1.767m 10.048ms 300 300 100.00
entropy_src_cfg_regwen 4.000s 61.241us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 1.767m 10.048ms 300 300 100.00
entropy_src_fw_ov 59.000s 5.135ms 300 300 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 88.437us 1000 1000 100.00
entropy_src_sec_cm 3.000s 187.991us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 88.437us 1000 1000 100.00
entropy_src_sec_cm 3.000s 187.991us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 1.767m 10.048ms 300 300 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 88.437us 1000 1000 100.00
entropy_src_sec_cm 3.000s 187.991us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 88.437us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 124.937us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 9.000s 392.841us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.717m 10.048ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2470 2470 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 10 10 10 100.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
89.07 98.33 95.94 99.28 94.85 97.92 94.00 82.52 38.59

Past Results