0c759b93ab
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | entropy_src_smoke | 4.000s | 23.931us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | entropy_src_csr_hw_reset | 5.000s | 54.822us | 5 | 5 | 100.00 |
V1 | csr_rw | entropy_src_csr_rw | 12.000s | 33.388us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | entropy_src_csr_bit_bash | 17.000s | 524.974us | 5 | 5 | 100.00 |
V1 | csr_aliasing | entropy_src_csr_aliasing | 12.000s | 182.769us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 12.000s | 24.791us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 12.000s | 33.388us | 20 | 20 | 100.00 |
entropy_src_csr_aliasing | 12.000s | 182.769us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | firmware | entropy_src_smoke | 4.000s | 23.931us | 50 | 50 | 100.00 |
entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 | ||
entropy_src_fw_ov | 2.033m | 5.098ms | 299 | 300 | 99.67 | ||
V2 | firmware_mode | entropy_src_fw_ov | 2.033m | 5.098ms | 299 | 300 | 99.67 |
V2 | rng_mode | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2 | rng_max_rate | entropy_src_rng_max_rate | 10.983m | 10.016ms | 399 | 400 | 99.75 |
V2 | health_checks | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2 | conditioning | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2 | interrupts | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2 | alerts | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_functional_alerts | 5.000s | 723.052us | 50 | 50 | 100.00 | ||
V2 | stress_all | entropy_src_stress_all | 12.000s | 280.529us | 50 | 50 | 100.00 |
V2 | functional_errors | entropy_src_functional_errors | 14.000s | 76.423us | 1000 | 1000 | 100.00 |
V2 | intr_test | entropy_src_intr_test | 14.000s | 61.088us | 50 | 50 | 100.00 |
V2 | alert_test | entropy_src_alert_test | 4.000s | 65.392us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 15.000s | 240.851us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | entropy_src_tl_errors | 15.000s | 240.851us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 5.000s | 54.822us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 12.000s | 33.388us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 12.000s | 182.769us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 10.000s | 71.472us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 5.000s | 54.822us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 12.000s | 33.388us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 12.000s | 182.769us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 10.000s | 71.472us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 2238 | 2240 | 99.91 | |||
V2S | tl_intg_err | entropy_src_sec_cm | 4.000s | 122.392us | 5 | 5 | 100.00 |
entropy_src_tl_intg_err | 19.000s | 199.780us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_cfg_regwen | 7.000s | 84.650us | 50 | 50 | 100.00 | ||
V2S | sec_cm_config_mubi | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_config_redun | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_intersig_mubi | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_fw_ov | 2.033m | 5.098ms | 299 | 300 | 99.67 | ||
V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 14.000s | 76.423us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 122.392us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 14.000s | 76.423us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 122.392us | 5 | 5 | 100.00 | ||
V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 10.883m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 14.000s | 76.423us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 122.392us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 14.000s | 76.423us | 1000 | 1000 | 100.00 |
V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 723.052us | 50 | 50 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 19.000s | 199.780us | 20 | 20 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 11.717m | 10.014ms | 50 | 50 | 100.00 |
V3 | stress_all_with_rand_reset | entropy_src_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 2468 | 2470 | 99.92 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 10 | 10 | 8 | 80.00 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 2 | 1 | 1 | 50.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.32 | 98.84 | 97.11 | 99.68 | 96.27 | 99.40 | 97.00 | 91.61 | 96.60 |
UVM_ERROR (entropy_src_scoreboard.sv:1836) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.err_code
has 1 failures:
226.entropy_src_fw_ov.4607221457285461186838292853352899781578629542305699381870698641105571063273
Line 419, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/226.entropy_src_fw_ov/latest/run.log
UVM_ERROR @ 1696557429 ps: (entropy_src_scoreboard.sv:1836) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 536870918 [0x20000006]) reg name: entropy_src_reg_block.err_code
UVM_INFO @ 1696557429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_scoreboard.sv:1836) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.alert_summary_fail_counts
has 1 failures:
335.entropy_src_rng_max_rate.94316820786630382538100902371330416208960351851343796970371889295965495803905
Line 1223, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/335.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 2876779332 ps: (entropy_src_scoreboard.sv:1836) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: entropy_src_reg_block.alert_summary_fail_counts
UVM_INFO @ 2876779332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---