ENTROPY_SRC Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 7.000s 150.941us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 7.000s 117.559us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 99.605us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 2.985ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 12.000s 835.288us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 11.000s 42.649us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 99.605us 20 20 100.00
entropy_src_csr_aliasing 12.000s 835.288us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 7.000s 150.941us 50 50 100.00
entropy_src_rng 11.633m 10.013ms 300 300 100.00
entropy_src_fw_ov 2.017m 5.049ms 300 300 100.00
V2 firmware_mode entropy_src_fw_ov 2.017m 5.049ms 300 300 100.00
V2 rng_mode entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 11.733m 10.015ms 398 400 99.50
V2 health_checks entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2 conditioning entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2 interrupts entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2 alerts entropy_src_rng 11.633m 10.013ms 300 300 100.00
entropy_src_functional_alerts 7.000s 124.225us 50 50 100.00
V2 stress_all entropy_src_stress_all 14.000s 246.091us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.000s 133.941us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 9.000s 49.774us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 51.726us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 606.561us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 606.561us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 7.000s 117.559us 5 5 100.00
entropy_src_csr_rw 8.000s 99.605us 20 20 100.00
entropy_src_csr_aliasing 12.000s 835.288us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 81.357us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 7.000s 117.559us 5 5 100.00
entropy_src_csr_rw 8.000s 99.605us 20 20 100.00
entropy_src_csr_aliasing 12.000s 835.288us 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 81.357us 20 20 100.00
V2 TOTAL 2238 2240 99.91
V2S tl_intg_err entropy_src_sec_cm 7.000s 243.954us 5 5 100.00
entropy_src_tl_intg_err 11.000s 214.676us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 11.633m 10.013ms 300 300 100.00
entropy_src_cfg_regwen 6.000s 19.521us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 11.633m 10.013ms 300 300 100.00
entropy_src_fw_ov 2.017m 5.049ms 300 300 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.000s 133.941us 1000 1000 100.00
entropy_src_sec_cm 7.000s 243.954us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.000s 133.941us 1000 1000 100.00
entropy_src_sec_cm 7.000s 243.954us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 11.633m 10.013ms 300 300 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.000s 133.941us 1000 1000 100.00
entropy_src_sec_cm 7.000s 243.954us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.000s 133.941us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 124.225us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 214.676us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 3.817m 10.054ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 3.251ms 44 50 88.00
TOTAL 2512 2520 99.68

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 9 90.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.35 98.84 97.11 99.68 96.27 99.40 97.00 91.61 96.80

Failure Buckets

Past Results