ENTROPY_SRC Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 10.000s 93.826us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 45.103us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 7.000s 53.531us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 2.769ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 1.160ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 7.000s 33.957us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 7.000s 53.531us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.160ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 10.000s 93.826us 50 50 100.00
entropy_src_rng 11.150m 10.012ms 299 300 99.67
entropy_src_fw_ov 2.167m 5.036ms 300 300 100.00
V2 firmware_mode entropy_src_fw_ov 2.167m 5.036ms 300 300 100.00
V2 rng_mode entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 13.000m 10.016ms 399 400 99.75
V2 health_checks entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2 conditioning entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2 interrupts entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2 alerts entropy_src_rng 11.150m 10.012ms 299 300 99.67
entropy_src_functional_alerts 11.000s 62.582us 50 50 100.00
V2 stress_all entropy_src_stress_all 17.000s 589.832us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.000s 40.395us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 5.000s 25.636us 50 50 100.00
V2 alert_test entropy_src_alert_test 7.000s 15.792us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 311.098us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 311.098us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 45.103us 5 5 100.00
entropy_src_csr_rw 7.000s 53.531us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.160ms 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 259.596us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 45.103us 5 5 100.00
entropy_src_csr_rw 7.000s 53.531us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.160ms 5 5 100.00
entropy_src_same_csr_outstanding 8.000s 259.596us 20 20 100.00
V2 TOTAL 2238 2240 99.91
V2S tl_intg_err entropy_src_sec_cm 10.000s 143.814us 5 5 100.00
entropy_src_tl_intg_err 10.000s 143.125us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 11.150m 10.012ms 299 300 99.67
entropy_src_cfg_regwen 10.000s 22.136us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 11.150m 10.012ms 299 300 99.67
entropy_src_fw_ov 2.167m 5.036ms 300 300 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.000s 40.395us 1000 1000 100.00
entropy_src_sec_cm 10.000s 143.814us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.000s 40.395us 1000 1000 100.00
entropy_src_sec_cm 10.000s 143.814us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 11.150m 10.012ms 299 300 99.67
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.000s 40.395us 1000 1000 100.00
entropy_src_sec_cm 10.000s 143.814us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.000s 40.395us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 11.000s 62.582us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 143.125us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.833m 10.026ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 19.000s 1.058ms 41 50 82.00
TOTAL 2509 2520 99.56

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 8 80.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.32 98.84 97.11 99.70 96.22 99.40 98.00 91.61 96.54

Failure Buckets

Past Results