ENTROPY_SRC Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 5.000s 23.269us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 39.256us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 153.500us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 20.000s 3.079ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 269.902us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 46.972us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 153.500us 20 20 100.00
entropy_src_csr_aliasing 9.000s 269.902us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 5.000s 23.269us 50 50 100.00
entropy_src_rng 4.400m 10.058ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.022ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 2.333m 5.022ms 299 300 99.67
V2 rng_mode entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 4.683m 10.090ms 400 400 100.00
V2 health_checks entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2 conditioning entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2 interrupts entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2 alerts entropy_src_rng 4.400m 10.058ms 299 300 99.67
entropy_src_functional_alerts 5.000s 103.493us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 254.066us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 15.000s 44.306us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 13.000s 99.345us 50 50 100.00
V2 alert_test entropy_src_alert_test 5.000s 36.847us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 138.894us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 138.894us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 39.256us 5 5 100.00
entropy_src_csr_rw 8.000s 153.500us 20 20 100.00
entropy_src_csr_aliasing 9.000s 269.902us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 210.927us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 39.256us 5 5 100.00
entropy_src_csr_rw 8.000s 153.500us 20 20 100.00
entropy_src_csr_aliasing 9.000s 269.902us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 210.927us 20 20 100.00
V2 TOTAL 2238 2240 99.91
V2S tl_intg_err entropy_src_sec_cm 5.000s 89.623us 5 5 100.00
entropy_src_tl_intg_err 13.000s 232.135us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.400m 10.058ms 299 300 99.67
entropy_src_cfg_regwen 5.000s 45.594us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.400m 10.058ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.022ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 15.000s 44.306us 1000 1000 100.00
entropy_src_sec_cm 5.000s 89.623us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 15.000s 44.306us 1000 1000 100.00
entropy_src_sec_cm 5.000s 89.623us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.400m 10.058ms 299 300 99.67
V2S sec_cm_ctr_redun entropy_src_functional_errors 15.000s 44.306us 1000 1000 100.00
entropy_src_sec_cm 5.000s 89.623us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 15.000s 44.306us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 103.493us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 13.000s 232.135us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.700m 10.048ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 31.000s 545.043us 48 50 96.00
TOTAL 2516 2520 99.84

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 8 80.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
85.92 98.85 97.17 99.69 95.92 89.26 97.00 91.70 52.88

Failure Buckets

Past Results