ENTROPY_SRC Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 68.470us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 26.917us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 35.972us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 3.180ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.058ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 51.199us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 35.972us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.058ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 68.470us 50 50 100.00
entropy_src_rng 12.500m 10.013ms 300 300 100.00
entropy_src_fw_ov 2.150m 5.076ms 300 300 100.00
V2 firmware_mode entropy_src_fw_ov 2.150m 5.076ms 300 300 100.00
V2 rng_mode entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 11.383m 10.014ms 400 400 100.00
V2 health_checks entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2 conditioning entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2 interrupts entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2 alerts entropy_src_rng 12.500m 10.013ms 300 300 100.00
entropy_src_functional_alerts 9.000s 117.492us 50 50 100.00
V2 stress_all entropy_src_stress_all 15.000s 174.894us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 50.341us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 4.000s 53.602us 50 50 100.00
V2 alert_test entropy_src_alert_test 11.000s 46.895us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 162.236us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 162.236us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 26.917us 5 5 100.00
entropy_src_csr_rw 3.000s 35.972us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.058ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 89.134us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 26.917us 5 5 100.00
entropy_src_csr_rw 3.000s 35.972us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.058ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 89.134us 20 20 100.00
V2 TOTAL 2240 2240 100.00
V2S tl_intg_err entropy_src_sec_cm 8.000s 50.916us 5 5 100.00
entropy_src_tl_intg_err 7.000s 682.738us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 12.500m 10.013ms 300 300 100.00
entropy_src_cfg_regwen 7.000s 44.078us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 12.500m 10.013ms 300 300 100.00
entropy_src_fw_ov 2.150m 5.076ms 300 300 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 50.341us 1000 1000 100.00
entropy_src_sec_cm 8.000s 50.916us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 50.341us 1000 1000 100.00
entropy_src_sec_cm 8.000s 50.916us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 12.500m 10.013ms 300 300 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 50.341us 1000 1000 100.00
entropy_src_sec_cm 8.000s 50.916us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 50.341us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 117.492us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 682.738us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 11.000m 10.013ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 35.000s 2.038ms 43 50 86.00
TOTAL 2513 2520 99.72

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 10 10 10 100.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.75 98.84 97.11 99.68 96.27 88.66 97.00 91.61 97.06

Failure Buckets

Past Results