ENTROPY_SRC Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: 7773b039d0

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 59.785us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 161.869us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 23.399us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 1.347ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 15.000s 152.787us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 74.128us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 23.399us 20 20 100.00
entropy_src_csr_aliasing 15.000s 152.787us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 59.785us 50 50 100.00
entropy_src_rng 4.950m 10.012ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.033ms 292 300 97.33
V2 firmware_mode entropy_src_fw_ov 2.450m 5.033ms 292 300 97.33
V2 rng_mode entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.900m 10.030ms 388 400 97.00
V2 health_checks entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2 conditioning entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2 interrupts entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2 alerts entropy_src_rng 4.950m 10.012ms 300 300 100.00
entropy_src_functional_alerts 18.000s 55.944us 50 50 100.00
V2 stress_all entropy_src_stress_all 20.000s 1.334ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 340.988us 50 50 100.00
V2 intr_test entropy_src_intr_test 13.000s 32.386us 50 50 100.00
V2 alert_test entropy_src_alert_test 18.000s 16.551us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 16.000s 838.185us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 16.000s 838.185us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 161.869us 5 5 100.00
entropy_src_csr_rw 8.000s 23.399us 20 20 100.00
entropy_src_csr_aliasing 15.000s 152.787us 5 5 100.00
entropy_src_same_csr_outstanding 14.000s 262.303us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 161.869us 5 5 100.00
entropy_src_csr_rw 8.000s 23.399us 20 20 100.00
entropy_src_csr_aliasing 15.000s 152.787us 5 5 100.00
entropy_src_same_csr_outstanding 14.000s 262.303us 20 20 100.00
V2 TOTAL 2245 2290 98.03
V2S tl_intg_err entropy_src_sec_cm 4.000s 489.954us 5 5 100.00
entropy_src_tl_intg_err 10.000s 198.593us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.950m 10.012ms 300 300 100.00
entropy_src_cfg_regwen 23.000s 41.399us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.950m 10.012ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.033ms 292 300 97.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
entropy_src_sec_cm 4.000s 489.954us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
entropy_src_sec_cm 4.000s 489.954us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.950m 10.012ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
entropy_src_sec_cm 4.000s 489.954us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
entropy_src_sec_cm 4.000s 489.954us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.333m 10.012ms 975 1000 97.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 18.000s 55.944us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 198.593us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.933m 10.026ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 33.000s 3.959ms 48 50 96.00
TOTAL 2523 2570 98.17

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.60 98.17 95.37 98.33 95.84 88.27 96.88 90.46 58.59

Failure Buckets

Past Results