ENTROPY_SRC Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 9.000s 38.102us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 12.000s 72.371us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 18.324us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 700.885us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 5.000s 43.428us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 59.247us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 18.324us 20 20 100.00
entropy_src_csr_aliasing 5.000s 43.428us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 9.000s 38.102us 50 50 100.00
entropy_src_rng 5.700m 10.063ms 299 300 99.67
entropy_src_fw_ov 2.800m 5.027ms 286 300 95.33
V2 firmware_mode entropy_src_fw_ov 2.800m 5.027ms 286 300 95.33
V2 rng_mode entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.800m 10.035ms 397 400 99.25
V2 health_checks entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2 conditioning entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2 interrupts entropy_src_rng 5.700m 10.063ms 299 300 99.67
entropy_src_intr 24.000s 13.495ms 50 50 100.00
V2 alerts entropy_src_rng 5.700m 10.063ms 299 300 99.67
entropy_src_functional_alerts 7.000s 206.854us 50 50 100.00
V2 stress_all entropy_src_stress_all 15.000s 1.411ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 677.252us 50 50 100.00
V2 intr_test entropy_src_intr_test 13.000s 20.365us 50 50 100.00
V2 alert_test entropy_src_alert_test 9.000s 21.666us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 9.000s 429.158us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 9.000s 429.158us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 12.000s 72.371us 5 5 100.00
entropy_src_csr_rw 3.000s 18.324us 20 20 100.00
entropy_src_csr_aliasing 5.000s 43.428us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 89.724us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 12.000s 72.371us 5 5 100.00
entropy_src_csr_rw 3.000s 18.324us 20 20 100.00
entropy_src_csr_aliasing 5.000s 43.428us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 89.724us 20 20 100.00
V2 TOTAL 2290 2340 97.86
V2S tl_intg_err entropy_src_sec_cm 8.000s 408.126us 5 5 100.00
entropy_src_tl_intg_err 11.000s 451.630us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.700m 10.063ms 299 300 99.67
entropy_src_cfg_regwen 4.000s 103.381us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.700m 10.063ms 299 300 99.67
entropy_src_fw_ov 2.800m 5.027ms 286 300 95.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
entropy_src_sec_cm 8.000s 408.126us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
entropy_src_sec_cm 8.000s 408.126us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.700m 10.063ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
entropy_src_sec_cm 8.000s 408.126us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
entropy_src_sec_cm 8.000s 408.126us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.567m 10.013ms 968 1000 96.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 206.854us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 451.630us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.933m 10.035ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2520 2570 98.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.13 98.15 95.32 98.33 95.79 96.71 96.88 90.48 95.85

Failure Buckets

Past Results