ENTROPY_SRC Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 91.747us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 411.163us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 13.736us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 701.922us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 11.000s 1.096ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 117.778us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 13.736us 20 20 100.00
entropy_src_csr_aliasing 11.000s 1.096ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 91.747us 50 50 100.00
entropy_src_rng 13.683m 20.049ms 299 300 99.67
entropy_src_fw_ov 13.767m 19.098ms 258 300 86.00
V2 firmware_mode entropy_src_fw_ov 13.767m 19.098ms 258 300 86.00
V2 rng_mode entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 25.167m 19.031ms 393 400 98.25
V2 health_checks entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2 conditioning entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2 interrupts entropy_src_rng 13.683m 20.049ms 299 300 99.67
entropy_src_intr 28.000s 13.211ms 50 50 100.00
V2 alerts entropy_src_rng 13.683m 20.049ms 299 300 99.67
entropy_src_functional_alerts 7.000s 80.073us 50 50 100.00
V2 stress_all entropy_src_stress_all 12.383m 20.221ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 41.000s 6.554ms 49 50 98.00
V2 intr_test entropy_src_intr_test 4.000s 12.306us 50 50 100.00
V2 alert_test entropy_src_alert_test 5.000s 22.557us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 10.000s 641.394us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 10.000s 641.394us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 411.163us 5 5 100.00
entropy_src_csr_rw 4.000s 13.736us 20 20 100.00
entropy_src_csr_aliasing 11.000s 1.096ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 322.638us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 411.163us 5 5 100.00
entropy_src_csr_rw 4.000s 13.736us 20 20 100.00
entropy_src_csr_aliasing 11.000s 1.096ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 322.638us 20 20 100.00
V2 TOTAL 2249 2340 96.11
V2S tl_intg_err entropy_src_sec_cm 5.000s 101.049us 5 5 100.00
entropy_src_tl_intg_err 7.000s 408.999us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 13.683m 20.049ms 299 300 99.67
entropy_src_cfg_regwen 5.000s 24.448us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 13.683m 20.049ms 299 300 99.67
entropy_src_fw_ov 13.767m 19.098ms 258 300 86.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
entropy_src_sec_cm 5.000s 101.049us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
entropy_src_sec_cm 5.000s 101.049us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 13.683m 20.049ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
entropy_src_sec_cm 5.000s 101.049us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
entropy_src_sec_cm 5.000s 101.049us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 12.050m 10.012ms 960 1000 96.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 80.073us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 408.999us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 11.533m 20.033ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
TOTAL 2478 2570 96.42

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 7 58.33
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.19 98.15 95.32 98.33 95.84 96.71 96.88 90.83 96.23

Failure Buckets

Past Results