FLASH_CTRL Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.611m	70.300us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.500s	125.508us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.490s	52.753us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.378m	12.472ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.101m	1.565ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.930s	103.593us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
		flash_ctrl_csr_aliasing	1.101m	1.565ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.710s	144.185us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.420s	27.567us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.390s	106.616us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.534m	55.347us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.378m	383.306ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.799m	540.430ms	20	20	100.00
		flash_ctrl_lcmgr_intg	15.420s	26.243us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.755m	248.593ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.464m	8.171ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.704m	2.605ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	47.896m	1.164s	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.263m	2.717ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	34.700s	58.854us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.330s	210.907us	40	40	100.00
		flash_ctrl_re_evict	40.160s	548.096us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.599m	5.506ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.599m	5.506ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.875m	45.423ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.480s	2.356ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.502m	879.212us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.314m	23.561ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.790m	1.864ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	41.947m	1.285ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.220s	15.052us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.841m	5.238ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	24.820s	13.330us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.880s	60.190us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.484m	1.650ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.895m	53.258ms	50	50	100.00
		flash_ctrl_otp_reset	2.425m	37.771us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.378m	383.306ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	7.724m	4.441ms	40	40	100.00
		flash_ctrl_intr_wr	2.024m	19.414ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	11.334m	131.426ms	39	40	97.50
		flash_ctrl_intr_wr_slow_flash	8.851m	89.789ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.616m	3.791ms	18	20	90.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	30.380s	2.118ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.990s	22.011us	5	5	100.00
		flash_ctrl_ro_derr	7.881m	24.500ms	10	10	100.00
		flash_ctrl_rw_derr	30.363m	29.247ms	10	10	100.00
		flash_ctrl_derr_detect	1.843m	569.398us	4	5	80.00
		flash_ctrl_integrity	30.274m	24.223ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.740s	106.615us	5	5	100.00
		flash_ctrl_ro_serr	6.461m	3.427ms	10	10	100.00
		flash_ctrl_rw_serr	32.498m	27.560ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.274m	2.766ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.548m	1.832ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.706m	11.050ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.190s	243.924us	1	1	100.00
		flash_ctrl_read_word_sweep	13.190s	14.305us	1	1	100.00
		flash_ctrl_ro	5.212m	3.887ms	20	20	100.00
		flash_ctrl_rw	27.320m	25.364ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.900s	2.708ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	19.224m	97.291ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.883m	10.013ms	19	20	95.00
V2	alert_test	flash_ctrl_alert_test	14.700s	153.751us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.480s	32.191us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.700s	193.325us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.700s	193.325us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.490s	52.753us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
		flash_ctrl_csr_aliasing	1.101m	1.565ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.230s	317.793us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.490s	52.753us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
		flash_ctrl_csr_aliasing	1.101m	1.565ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.230s	317.793us	20	20	100.00
V2		TOTAL			1006	1013	99.31
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.757m	411.946us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.270m	1.486ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.270m	1.486ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.270m	1.486ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.770s	109.197us	3	3	100.00
		flash_ctrl_wr_intg	15.020s	47.371us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.611m	70.300us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.425m	37.771us	80	80	100.00
		flash_ctrl_disable	24.820s	13.330us	50	50	100.00
		flash_ctrl_sec_info_access	1.525m	8.506ms	50	50	100.00
		flash_ctrl_connect	17.880s	60.190us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.950s	60.031us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.610s	506.795us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.969m	47.601us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	24.820s	13.330us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.770s	109.197us	3	3	100.00
		flash_ctrl_access_after_disable	13.980s	13.853us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	24.820s	13.330us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.480s	2.356ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	27.320m	25.364ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	32.498m	27.560ms	10	10	100.00
		flash_ctrl_rw_derr	30.363m	29.247ms	10	10	100.00
		flash_ctrl_integrity	30.274m	24.223ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.378m	383.306ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	16.780s	23.588us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.790s	163.994us	2	5	40.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.110s	13.340us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.372h	2.084ms	5	5	100.00
V2S		TOTAL			139	144	96.53
V3	asymmetric_read_path	flash_ctrl_rd_ooo	52.670s	111.238us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1266	1278	99.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	12	12	9	75.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.42	95.49	94.29	98.95	91.84	97.32	98.30	98.78

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_derr_detect has 1 failures.

1.flash_ctrl_derr_detect.1173600745
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 287491.1 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 287491.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_invalid_op has 2 failures.

2.flash_ctrl_invalid_op.2526273675
Line 692, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 355447.1 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 355447.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_invalid_op.1215064928
Line 5580, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 3683056.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3683056.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(mem_tl_o.d_valid))' has 2 failures:

Test flash_ctrl_phy_host_grant_err has 2 failures.

0.flash_ctrl_phy_host_grant_err.1691939045
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 25280.9 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 25280.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_phy_host_grant_err.1976057256
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 6038.4 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 6038.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test flash_ctrl_full_mem_access has 2 failures.
  - 3.flash_ctrl_full_mem_access.1468506463
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:44a31127-8254-41a4-85f5-3c4e903637c6
```
  - 4.flash_ctrl_full_mem_access.2184905192
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:7948654d-2389-4f32-bb61-5663c5bf7d2a
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_std_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.1201949981
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 13340.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_std_err triggered unexpectedly
  UVM_INFO @ 13340.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank1] *: obs:exp ff_*_4cfae3b5_ffffffff:*_*_73c758d7_1d01ac* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 2.flash_ctrl_wr_intg.3348142156
    Line 273, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 76074.7 ns: (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank1]    0: obs:exp    ff_6_4cfae3b5_ffffffff:02_6_73c758d7_1d01ac64  mismatch!!
  UVM_INFO @ 76074.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 1 failures:
- Test flash_ctrl_intr_rd_slow_flash has 1 failures.
  - 3.flash_ctrl_intr_rd_slow_flash.1598357039
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 4.flash_ctrl_phy_host_grant_err.3383886797
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 10213.5 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 10213.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 1 failures.
  - 17.flash_ctrl_hw_prog_rma_wipe_err.568199059
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10005587.7 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28875 [0x70cb])
  UVM_INFO @ 10005587.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```