Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.40 100.00 86.21 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.18 100.00 90.91 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.87 100.00 91.51 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_gf_mult.u_mult 100.00 100.00 100.00 100.00 100.00
gen_prince.u_cipher 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.40 100.00 86.21 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.18 100.00 90.91 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 83.96 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_gf_mult.u_mult 100.00 100.00 100.00 100.00 100.00
gen_prince.u_cipher 100.00 100.00

Line Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
TOTAL1818100.00
ALWAYS4344100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN8911100.00
ALWAYS9644100.00
ALWAYS11233100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
45 1 1
46 1 1
MISSING_ELSE
50 1 1
53 1 1
89 1 1
96 1 1
97 1 1
98 1 1
99 1 1
MISSING_ELSE
112 1 1
113 1 1
115 1 1
119 1 1
120 1 1
155 1 1
158 1 1


Cond Coverage for Module : flash_phy_scramble
TotalCoveredPercent
Conditions292586.21
Logical292586.21
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT1,T2,T3
10CoveredT1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 50 2 2 100.00
TERNARY 119 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 158 2 2 100.00
TERNARY 132 2 2 100.00
TERNARY 132 2 2 100.00
IF 43 3 3 100.00
IF 96 3 3 100.00
IF 112 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 119 (op_ack_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 158 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 132 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 132 (data_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 45 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 96 if ((!rst_ni)) -2-: 98 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1818100.00
ALWAYS4344100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN8911100.00
ALWAYS9644100.00
ALWAYS11233100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
45 1 1
46 1 1
MISSING_ELSE
50 1 1
53 1 1
89 1 1
96 1 1
97 1 1
98 1 1
99 1 1
MISSING_ELSE
112 1 1
113 1 1
115 1 1
119 1 1
120 1 1
155 1 1
158 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
TotalCoveredPercent
Conditions292586.21
Logical292586.21
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT1,T2,T3
10CoveredT1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 50 2 2 100.00
TERNARY 119 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 158 2 2 100.00
TERNARY 132 2 2 100.00
TERNARY 132 2 2 100.00
IF 43 3 3 100.00
IF 96 3 3 100.00
IF 112 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 119 (op_ack_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 158 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 132 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 132 (data_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 45 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 96 if ((!rst_ni)) -2-: 98 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1818100.00
ALWAYS4344100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN8911100.00
ALWAYS9644100.00
ALWAYS11233100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
45 1 1
46 1 1
MISSING_ELSE
50 1 1
53 1 1
89 1 1
96 1 1
97 1 1
98 1 1
99 1 1
MISSING_ELSE
112 1 1
113 1 1
115 1 1
119 1 1
120 1 1
155 1 1
158 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
TotalCoveredPercent
Conditions292586.21
Logical292586.21
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T10
01UnreachableT1,T2,T10
10CoveredT1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T10
11UnreachableT1,T2,T10

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T10
01CoveredT1,T2,T10
10CoveredT1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T10
11CoveredT1,T2,T10

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T10

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T10

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T10

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0CoveredT2,T5,T84
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0CoveredT2,T5,T84
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0CoveredT2,T5,T84
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 50 2 2 100.00
TERNARY 119 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 158 2 2 100.00
TERNARY 132 2 2 100.00
TERNARY 132 2 2 100.00
IF 43 3 3 100.00
IF 96 3 3 100.00
IF 112 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 50 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 119 (op_ack_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T84


LineNo. Expression -1-: 158 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T84


LineNo. Expression -1-: 132 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T5,T84


LineNo. Expression -1-: 132 (data_key_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 45 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T10


LineNo. Expression -1-: 96 if ((!rst_ni)) -2-: 98 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T10


LineNo. Expression -1-: 112 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%