SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher | 100.00 | 100.00 | |||||
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.40 | 100.00 | 86.21 | 100.00 | u_scramble |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.40 | 100.00 | 86.21 | 100.00 | u_scramble |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 522 | 522 | 100.00 |
Total Bits 0->1 | 261 | 261 | 100.00 |
Total Bits 1->0 | 261 | 261 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 522 | 522 | 100.00 |
Port Bits 0->1 | 261 | 261 | 100.00 |
Port Bits 1->0 | 261 | 261 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T10 | Yes | T1,T2,T3 | INPUT |
valid_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
data_i[63:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
key_i[127:0] | Yes | Yes | T1,T2,T3 | Yes | T2,T3,T7 | INPUT |
dec_i | Yes | Yes | T1,T2,T5 | Yes | T1,T2,T5 | INPUT |
valid_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
data_o[63:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 522 | 522 | 100.00 |
Total Bits 0->1 | 261 | 261 | 100.00 |
Total Bits 1->0 | 261 | 261 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 522 | 522 | 100.00 |
Port Bits 0->1 | 261 | 261 | 100.00 |
Port Bits 1->0 | 261 | 261 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T10 | Yes | T1,T2,T3 | INPUT |
valid_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
data_i[63:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
key_i[127:0] | Yes | Yes | T1,T2,T3 | Yes | T2,T3,T7 | INPUT |
dec_i | Yes | Yes | T1,T2,T5 | Yes | T1,T2,T5 | INPUT |
valid_o | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
data_o[63:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 522 | 522 | 100.00 |
Total Bits 0->1 | 261 | 261 | 100.00 |
Total Bits 1->0 | 261 | 261 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 522 | 522 | 100.00 |
Port Bits 0->1 | 261 | 261 | 100.00 |
Port Bits 1->0 | 261 | 261 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T10 | Yes | T1,T2,T3 | INPUT |
valid_i | Yes | Yes | T1,T2,T10 | Yes | T1,T2,T10 | INPUT |
data_i[63:0] | Yes | Yes | T1,T2,T10 | Yes | T1,T2,T10 | INPUT |
key_i[127:0] | Yes | Yes | T1,T2,T3 | Yes | T2,T3,T7 | INPUT |
dec_i | Yes | Yes | T2,T5,T84 | Yes | T2,T5,T84 | INPUT |
valid_o | Yes | Yes | T1,T2,T10 | Yes | T1,T2,T10 | OUTPUT |
data_o[63:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |