Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_rd_fifo.u_err	66.91	76.92	65.71			25.00	100.00
tb.dut.u_tl_adapter_eflash.u_err	73.63	88.46	68.57			37.50	100.00
tb.dut.u_to_prog_fifo.u_err	87.32	100.00	74.29			75.00	100.00
tb.dut.u_reg_core.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_to_rd_fifo.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.91	76.92	65.71			25.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.91	76.92	65.71			25.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.86	100.00	79.13			96.30	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.63	88.46	68.57			37.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.63	88.46	68.57			37.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	83.62			96.30	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_prog_fifo.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.32	100.00	74.29			75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.32	100.00	74.29			75.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.25	100.00	66.67			84.62	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.96	100.00	91.84			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T16,T48,T49
0	0	1	Covered	T48,T49,T53
0	1	0	Covered	T49,T53,T54
1	0	0	Covered	T48,T49,T51

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T49,T53,T54
1	0	Covered	T48,T49,T51
1	1	Covered	T16,T48,T49

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T48,T49,T53
0	0	1	Covered	T16,T48,T49
0	1	0	Covered	T16,T48,T49
1	0	0	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T48,T49,T53
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T48,T49,T53
1	1	1	Covered	T16,T48,T49

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T48,T49,T51
0	0	1	Covered	T16,T48,T49
0	1	0	Covered	T16,T48,T49
1	0	0	Covered	T16,T48,T49

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T16,T48,T49
1	'h1	1	-	Covered	T16,T48,T49
1	'h1	0	-	Covered	T16,T48,T49
1	'h1	-	1	Covered	T16,T48,T49
1	'h1	-	0	Covered	T16,T48,T49
1	'h00000002	-	-	Covered	T16,T48,T49
1	default	-	-	Covered	T49,T53,T54
0	-	-	-	Covered	T16,T48,T49

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	5674	5674	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5674	5674	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T8	3	3	0	0
T10	3	3	0	0
T16	2	2	0	0
T20	3	3	0	0
T21	3	3	0	0
T48	2	2	0	0
T49	2	2	0	0
T51	2	2	0	0
T52	2	2	0	0
T53	2	2	0	0
T54	2	2	0	0
T55	2	2	0	0
T56	2	2	0	0
T57	2	2	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	20	76.92
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	11	64.71
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	0	1
64	0	1
65	0	1
69	0	1
71	0	1
73	0	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_err

	Total	Covered	Percent
Conditions	35	23	65.71
Logical	35	23	65.71
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T6
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_err

	Line No.	Total	Covered	Percent
Branches		8	2	25.00
IF	60	8	2	25.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Not Covered
1	'h1	1	-	Not Covered
1	'h1	0	-	Not Covered
1	'h1	-	1	Not Covered
1	'h1	-	0	Not Covered
1	'h00000002	-	-	Covered	T1,T4,T6
1	default	-	-	Not Covered
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1052	1052	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	23	88.46
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	14	82.35
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	0	1
71	0	1
73	0	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err

	Total	Covered	Percent
Conditions	35	24	68.57
Logical	35	24	68.57
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T8

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T10,T8
0	0	1	Covered	T36,T37,T38
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T35

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T8

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Covered	T1,T10,T8
0	1	0	Covered	T1,T2,T7
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T8

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T8

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T7
1	0	0	Covered	T1,T35,T7

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err

	Line No.	Total	Covered	Percent
Branches		8	3	37.50
IF	60	8	3	37.50

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T14,T15
1	'h1	1	-	Not Covered
1	'h1	0	-	Not Covered
1	'h1	-	1	Not Covered
1	'h1	-	0	Not Covered
1	'h00000002	-	-	Covered	T1,T10,T8
1	default	-	-	Not Covered
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1052	1052	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_err

	Total	Covered	Percent
Conditions	35	26	74.29
Logical	35	26	74.29
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T5
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T15
1	Not Covered

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T15
1	Not Covered

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_err

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	60	8	6	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T14,T15
1	'h1	1	-	Not Covered
1	'h1	0	-	Covered	T15
1	'h1	-	1	Not Covered
1	'h1	-	0	Covered	T15
1	'h00000002	-	-	Covered	T1,T4,T5
1	default	-	-	Covered	T14,T15
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1052	1052	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T16,T48,T49
0	0	1	Covered	T48,T49,T53
0	1	0	Covered	T49,T53,T54
1	0	0	Covered	T48,T49,T51

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T53,T54,T138
1	0	Covered	T48,T49,T51
1	1	Covered	T16,T48,T49

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T48,T53,T54
0	0	1	Covered	T16,T48,T49
0	1	0	Covered	T16,T48,T49
1	0	0	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T48,T53,T54
1	0	1	Covered	T48,T53,T54
1	1	0	Covered	T48,T53,T54
1	1	1	Covered	T16,T48,T49

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T48,T49,T51
0	0	1	Covered	T16,T48,T49
0	1	0	Covered	T16,T48,T49
1	0	0	Covered	T16,T48,T49

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T16,T48,T49
1	'h1	1	-	Covered	T16,T48,T49
1	'h1	0	-	Covered	T16,T48,T49
1	'h1	-	1	Covered	T16,T48,T49
1	'h1	-	0	Covered	T16,T48,T49
1	'h00000002	-	-	Covered	T16,T48,T49
1	default	-	-	Covered	T53,T54,T138
0	-	-	-	Covered	T16,T48,T49

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1259	1259	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T52

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T51

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T51

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T48,T49,T53
0	0	1	Covered	T48,T49,T53
0	1	0	Covered	T49,T53,T54
1	0	0	Covered	T48,T49,T51

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T49,T53,T54
1	0	Covered	T48,T49,T51
1	1	Covered	T48,T49,T53

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T49,T53,T54
0	0	1	Covered	T48,T49,T51
0	1	0	Covered	T48,T49,T51
1	0	0	Covered	T48,T49,T52

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T52

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T51

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T48,T49,T51

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T48,T49,T53
1	Covered	T48,T49,T53

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T48,T49,T53
1	Covered	T48,T49,T53

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T48,T49,T53
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T49,T53,T54
1	1	1	Covered	T48,T49,T53

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T49,T52,T53
0	0	1	Covered	T48,T49,T53
0	1	0	Covered	T48,T49,T51
1	0	0	Covered	T48,T49,T51

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T48,T49,T53
1	'h1	1	-	Covered	T48,T49,T53
1	'h1	0	-	Covered	T48,T49,T53
1	'h1	-	1	Covered	T48,T49,T53
1	'h1	-	0	Covered	T48,T49,T53
1	'h00000002	-	-	Covered	T48,T49,T53
1	default	-	-	Covered	T49,T53,T54
0	-	-	-	Covered	T48,T49,T51

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1259	1259	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0