Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.25 100.00 66.67 84.62 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.40 89.33 64.86 82.14 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 87.32 100.00 74.29 75.00 100.00
u_reqfifo 91.88 100.00 73.08 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 68.01 91.43 51.85 68.75 60.00
u_sram_byte 100.00 100.00
u_sramreqfifo 70.88 94.44 47.83 81.25 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.86 100.00 79.13 96.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.01 88.89 76.99 100.00 89.16 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 91.88 100.00 73.08 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 97.84 100.00 89.19 100.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 90.92 100.00 69.23 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.98 100.00 83.62 96.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.20 91.60 81.01 100.00 93.41 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 73.63 88.46 68.57 37.50 100.00
u_reqfifo 95.19 100.00 80.77 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 96.32 100.00 85.29 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 95.19 100.00 80.77 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
84.25 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL6161100.00
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
93.86 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
94.98 100.00
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
84.25 66.67
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1117466.67
Logical1117466.67
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T24
10CoveredT1,T2,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T22,T23
11CoveredT1,T4,T5

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T9,T25
11CoveredT1,T4,T5

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T9,T25
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT1,T2,T3
10CoveredT1,T4,T5

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T4,T5

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T5

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
93.86 79.13
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1159179.13
Logical1159179.13
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T18,T19
010CoveredT17,T18,T19
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T24
10CoveredT1,T2,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T4,T6

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T23,T24
11CoveredT1,T4,T6

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T8,T9
11CoveredT1,T4,T6

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14
1CoveredT1,T4,T6

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14
1CoveredT1,T4,T6

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T6
01Not Covered
10CoveredT26,T27,T28

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T4,T6

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT26,T27,T28
11CoveredT1,T4,T6

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT26,T27,T28

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T8,T9
101CoveredT23,T29,T30
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T8,T9
01CoveredT1,T2,T3
10CoveredT1,T4,T6

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T6

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T6
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT23,T29,T30
10Not Covered
11CoveredT1,T4,T6

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
94.98 83.62
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions1169783.62
Logical1169783.62
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT31,T32,T33

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT31,T32,T33
010Unreachable
100CoveredT31,T32,T33

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T10,T8
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T10,T8
01CoveredT1,T2,T7
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T23,T24
01CoveredT1,T23,T24
10CoveredT1,T7,T34

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T7
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T7,T34
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T10,T8
000001CoveredT31,T32,T33
000010CoveredT1,T35,T7
000100CoveredT36,T37,T38
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T8,T9
11CoveredT1,T10,T8

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T7,T24
11CoveredT1,T10,T8

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T8,T9
11CoveredT1,T10,T8

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T10,T8

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T10,T8

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T10,T8
01CoveredT36,T37,T38
10CoveredT39,T40,T41

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT36,T37,T38
1110Not Covered
1111CoveredT1,T10,T8

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T40,T41
11CoveredT1,T10,T8

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT1,T10,T8
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T8
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T10,T8
11CoveredT39,T40,T41

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T8,T9
101CoveredT37,T42,T43
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T8,T9
01CoveredT1,T2,T3
10CoveredT1,T10,T8

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T8,T9
110CoveredT36,T37,T38
111CoveredT1,T10,T8

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T8
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T10,T8
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T10,T8
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T10,T8
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T10,T8

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T10,T8
10Not Covered
11CoveredT1,T10,T8

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T37,T38
11CoveredT1,T10,T8

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T36,T37,T38
1 0 1 Covered T1,T4,T6
1 0 0 Covered T1,T4,T5
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T6
1 0 Covered T1,T4,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1237684959 1235402088 0 0
DataIntgOptions_A 3156 3156 0 0
ReqOutKnown_A 1237684959 1235402088 0 0
SramDwHasByteGranularity_A 3156 3156 0 0
SramDwIsMultipleOfTlulWidth_A 3156 3156 0 0
TlOutKnown_A 1237684959 1235402088 0 0
TlOutPayloadKnown_A 1237684959 11908679 0 0
TlOutPayloadKnown_AKnownEnable 1237684959 1235402088 0 0
WdataOutKnown_A 1237684959 1235402088 0 0
WeOutKnown_A 1237684959 1235402088 0 0
WmaskOutKnown_A 1237684959 1235402088 0 0
adapterNoReadOrWrite 3156 3156 0 0
rvalidHighReqFifoEmpty 1237684959 7023800 0 0
rvalidHighWhenRspFifoFull 1237040559 7017465 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3156 3156 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T8 3 3 0 0
T10 3 3 0 0
T20 3 3 0 0
T21 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3156 3156 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T8 3 3 0 0
T10 3 3 0 0
T20 3 3 0 0
T21 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3156 3156 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T8 3 3 0 0
T10 3 3 0 0
T20 3 3 0 0
T21 3 3 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 11908679 0 0
T1 1006161 57652 0 0
T2 1201302 0 0 0
T3 10179 0 0 0
T4 145614 9728 0 0
T5 218742 4144 0 0
T6 3159 14 0 0
T7 0 518 0 0
T8 136314 21815 0 0
T9 0 388 0 0
T10 42696 251 0 0
T20 3300 0 0 0
T21 2832 0 0 0
T22 0 6142 0 0
T23 0 25732 0 0
T24 0 16723 0 0
T25 0 9216 0 0
T44 0 16862 0 0
T45 0 50545 0 0
T46 0 51000 0 0
T47 0 40567 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 1235402088 0 0
T1 1006161 1005864 0 0
T2 1201302 1201254 0 0
T3 10179 8400 0 0
T4 145614 145410 0 0
T5 218742 218445 0 0
T6 3159 2958 0 0
T8 136314 136125 0 0
T10 42696 42375 0 0
T20 3300 3051 0 0
T21 2832 2682 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 3156 3156 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T8 3 3 0 0
T10 3 3 0 0
T20 3 3 0 0
T21 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237684959 7023800 0 0
T1 670774 48811 0 0
T2 800868 0 0 0
T3 6786 0 0 0
T4 97076 6144 0 0
T5 145828 1963 0 0
T6 2106 14 0 0
T7 0 275 0 0
T8 90876 21815 0 0
T9 0 322 0 0
T10 28464 251 0 0
T20 2200 0 0 0
T21 1888 0 0 0
T23 0 3752 0 0
T24 0 16723 0 0
T25 0 4608 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0
T47 0 40567 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1237040559 7017465 0 0
T1 670774 48811 0 0
T2 800868 0 0 0
T3 6786 0 0 0
T4 97076 6144 0 0
T5 145828 1963 0 0
T6 2106 14 0 0
T7 0 275 0 0
T8 90876 21815 0 0
T9 0 322 0 0
T10 28464 251 0 0
T20 2200 0 0 0
T21 1888 0 0 0
T23 0 3752 0 0
T24 0 16723 0 0
T25 0 4608 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0
T47 0 40567 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL6161100.00
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1117466.67
Logical1117466.67
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T24
10CoveredT1,T2,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T22,T23
11CoveredT1,T4,T5

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T9,T25
11CoveredT1,T4,T5

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T9,T25
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT1,T2,T3
10CoveredT1,T4,T5

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T4,T5

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T5

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 26 22 84.62
TERNARY 107 2 2 100.00
TERNARY 291 2 1 50.00
TERNARY 297 3 1 33.33
TERNARY 324 2 2 100.00
TERNARY 447 2 1 50.00
IF 93 2 2 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T14,T15
1 0 1 Covered T14,T15
1 0 0 Covered T1,T4,T5
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T14,T15
1 0 Covered T1,T4,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T14,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 12 85.71
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 12 85.71




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 412561653 411800696 0 0
DataIntgOptions_A 1052 1052 0 0
ReqOutKnown_A 412561653 411800696 0 0
SramDwHasByteGranularity_A 1052 1052 0 0
SramDwIsMultipleOfTlulWidth_A 1052 1052 0 0
TlOutKnown_A 412561653 411800696 0 0
TlOutPayloadKnown_A 412561653 2899904 0 0
TlOutPayloadKnown_AKnownEnable 412561653 411800696 0 0
WdataOutKnown_A 412561653 411800696 0 0
WeOutKnown_A 412561653 411800696 0 0
WmaskOutKnown_A 412561653 411800696 0 0
adapterNoReadOrWrite 1052 1052 0 0
rvalidHighReqFifoEmpty 412561653 0 0 0
rvalidHighWhenRspFifoFull 412561653 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 2899904 0 0
T1 335387 8841 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 3584 0 0
T5 72914 2181 0 0
T6 1053 0 0 0
T7 0 243 0 0
T8 45438 0 0 0
T9 0 66 0 0
T10 14232 0 0 0
T20 1100 0 0 0
T21 944 0 0 0
T22 0 6142 0 0
T23 0 8853 0 0
T25 0 4608 0 0
T45 0 8812 0 0
T46 0 9238 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1159179.13
Logical1159179.13
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T18,T19
010CoveredT17,T18,T19
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T24
10CoveredT1,T2,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T4,T6

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T23,T24
11CoveredT1,T4,T6

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T8,T9
11CoveredT1,T4,T6

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14
1CoveredT1,T4,T6

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14
1CoveredT1,T4,T6

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T6
01Not Covered
10CoveredT26,T27,T28

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T4,T6

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT26,T27,T28
11CoveredT1,T4,T6

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT26,T27,T28

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T8,T9
101CoveredT23,T29,T30
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T8,T9
01CoveredT1,T2,T3
10CoveredT1,T4,T6

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T6

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T6
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT23,T29,T30
10Not Covered
11CoveredT1,T4,T6

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T14
1 0 1 Covered T1,T4,T6
1 0 0 Covered T14
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T6
1 0 Covered T14
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 412561653 411800696 0 0
DataIntgOptions_A 1052 1052 0 0
ReqOutKnown_A 412561653 411800696 0 0
SramDwHasByteGranularity_A 1052 1052 0 0
SramDwIsMultipleOfTlulWidth_A 1052 1052 0 0
TlOutKnown_A 412561653 411800696 0 0
TlOutPayloadKnown_A 412561653 4141198 0 0
TlOutPayloadKnown_AKnownEnable 412561653 411800696 0 0
WdataOutKnown_A 412561653 411800696 0 0
WeOutKnown_A 412561653 411800696 0 0
WmaskOutKnown_A 412561653 411800696 0 0
adapterNoReadOrWrite 1052 1052 0 0
rvalidHighReqFifoEmpty 412561653 2826141 0 0
rvalidHighWhenRspFifoFull 411917253 2819806 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4141198 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 16879 0 0
T25 0 4608 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 2826141 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 3752 0 0
T25 0 4608 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 411917253 2819806 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 3752 0 0
T25 0 4608 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS22988100.00
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions1169783.62
Logical1169783.62
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT31,T32,T33

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT31,T32,T33
010Unreachable
100CoveredT31,T32,T33

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T10,T8
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T10,T8
01CoveredT1,T2,T7
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T7

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T23,T24
01CoveredT1,T23,T24
10CoveredT1,T7,T34

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T7
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T7,T34
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T10,T8
000001CoveredT31,T32,T33
000010CoveredT1,T35,T7
000100CoveredT36,T37,T38
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T8,T9
11CoveredT1,T10,T8

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T7,T24
11CoveredT1,T10,T8

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T8,T9
11CoveredT1,T10,T8

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T10,T8

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT14,T15
1CoveredT1,T10,T8

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T10,T8
01CoveredT36,T37,T38
10CoveredT39,T40,T41

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT36,T37,T38
1110Not Covered
1111CoveredT1,T10,T8

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T40,T41
11CoveredT1,T10,T8

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT1,T10,T8
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T8
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T10,T8
11CoveredT39,T40,T41

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T8,T9
101CoveredT37,T42,T43
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T8,T9
01CoveredT1,T2,T3
10CoveredT1,T10,T8

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T8,T9
110CoveredT36,T37,T38
111CoveredT1,T10,T8

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T8
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T10,T8
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T10,T8
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T10,T8
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T10,T8

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T10,T8
10Not Covered
11CoveredT1,T10,T8

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T37,T38
11CoveredT1,T10,T8

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T8

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T10,T8


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T10,T8
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T31,T32,T33
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T36,T37,T38
1 0 1 Covered T1,T10,T8
1 0 0 Covered T14,T15
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T10,T8
1 0 Covered T14,T15
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T10,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 412561653 411800696 0 0
DataIntgOptions_A 1052 1052 0 0
ReqOutKnown_A 412561653 411800696 0 0
SramDwHasByteGranularity_A 1052 1052 0 0
SramDwIsMultipleOfTlulWidth_A 1052 1052 0 0
TlOutKnown_A 412561653 411800696 0 0
TlOutPayloadKnown_A 412561653 4867577 0 0
TlOutPayloadKnown_AKnownEnable 412561653 411800696 0 0
WdataOutKnown_A 412561653 411800696 0 0
WeOutKnown_A 412561653 411800696 0 0
WmaskOutKnown_A 412561653 411800696 0 0
adapterNoReadOrWrite 1052 1052 0 0
rvalidHighReqFifoEmpty 412561653 4197659 0 0
rvalidHighWhenRspFifoFull 412561653 4197659 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4867577 0 0
T1 335387 41367 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 0 0 0
T7 0 10 0 0
T8 45438 16489 0 0
T9 0 229 0 0
T10 14232 15 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 16723 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0
T47 0 40567 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4197659 0 0
T1 335387 41367 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 0 0 0
T7 0 10 0 0
T8 45438 16489 0 0
T9 0 229 0 0
T10 14232 15 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 16723 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0
T47 0 40567 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4197659 0 0
T1 335387 41367 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 0 0 0
T7 0 10 0 0
T8 45438 16489 0 0
T9 0 229 0 0
T10 14232 15 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 16723 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0
T47 0 40567 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%