Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1650246612	1647202784	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1650246612	434887005	0	0
GntImpliesValid_A	1650246612	434887005	0	0
GrantKnown_A	1650246612	1647202784	0	0
IdxKnown_A	1650246612	1647202784	0	0
IndexIsCorrect_A	1650246612	434887005	0	0
NoReadyValidNoGrant_A	1650246612	178019235	0	0
Priority_A	1650246612	459372540	0	0
ReadyAndValidImplyGrant_A	1650246612	434887005	0	0
ReqAndReadyImplyGrant_A	1650246612	434887005	0	0
ReqImpliesValid_A	1650246612	459372540	0	0
ValidKnown_A	1650246612	1647202784	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	1647202784	0	0
T1	1341548	1341152	0	0
T2	1601736	1601672	0	0
T3	13572	11200	0	0
T4	194152	193880	0	0
T5	291656	291260	0	0
T6	4212	3944	0	0
T8	181752	181500	0	0
T10	56928	56500	0	0
T20	4400	4068	0	0
T21	3776	3576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T8	4	4	0	0
T10	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	434887005	0	0
T1	1341548	456988	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	43694	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	28284	0	0
T44	0	31674	0	0
T84	0	255794	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	434887005	0	0
T1	1341548	456988	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	43694	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	28284	0	0
T44	0	31674	0	0
T84	0	255794	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	1647202784	0	0
T1	1341548	1341152	0	0
T2	1601736	1601672	0	0
T3	13572	11200	0	0
T4	194152	193880	0	0
T5	291656	291260	0	0
T6	4212	3944	0	0
T8	181752	181500	0	0
T10	56928	56500	0	0
T20	4400	4068	0	0
T21	3776	3576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	1647202784	0	0
T1	1341548	1341152	0	0
T2	1601736	1601672	0	0
T3	13572	11200	0	0
T4	194152	193880	0	0
T5	291656	291260	0	0
T6	4212	3944	0	0
T8	181752	181500	0	0
T10	56928	56500	0	0
T20	4400	4068	0	0
T21	3776	3576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	434887005	0	0
T1	1341548	456988	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	43694	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	28284	0	0
T44	0	31674	0	0
T84	0	255794	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	178019235	0	0
T1	1341548	190320	0	0
T2	1601736	2109952	0	0
T3	13572	1324	0	0
T4	194152	2688	0	0
T5	291656	7758	0	0
T6	4212	332	0	0
T8	181752	57922	0	0
T9	0	440	0	0
T10	56928	1782	0	0
T20	4400	256	0	0
T21	3776	256	0	0
T24	0	74718	0	0
T44	0	85274	0	0
T45	0	69414	0	0
T84	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	459372540	0	0
T1	1341548	524576	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	54722	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	30400	0	0
T44	0	33816	0	0
T84	0	255794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	434887005	0	0
T1	1341548	456988	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	43694	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	28284	0	0
T44	0	31674	0	0
T84	0	255794	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	434887005	0	0
T1	1341548	456988	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	43694	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	28284	0	0
T44	0	31674	0	0
T84	0	255794	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	459372540	0	0
T1	1341548	524576	0	0
T2	1601736	514650	0	0
T3	13572	350	0	0
T4	194152	29184	0	0
T5	291656	111396	0	0
T6	4212	92	0	0
T8	181752	54722	0	0
T9	0	1358	0	0
T10	56928	20910	0	0
T20	4400	64	0	0
T21	3776	64	0	0
T22	0	12738	0	0
T24	0	30400	0	0
T44	0	33816	0	0
T84	0	255794	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650246612	1647202784	0	0
T1	1341548	1341152	0	0
T2	1601736	1601672	0	0
T3	13572	11200	0	0
T4	194152	193880	0	0
T5	291656	291260	0	0
T6	4212	3944	0	0
T8	181752	181500	0	0
T10	56928	56500	0	0
T20	4400	4068	0	0
T21	3776	3576	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T8,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T8,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T8,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T8,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412561653	411800696	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	412561653	118416734	0	0
GntImpliesValid_A	412561653	118416734	0	0
GrantKnown_A	412561653	411800696	0	0
IdxKnown_A	412561653	411800696	0	0
IndexIsCorrect_A	412561653	118416734	0	0
NoReadyValidNoGrant_A	412561653	46745204	0	0
Priority_A	412561653	124722535	0	0
ReadyAndValidImplyGrant_A	412561653	118416734	0	0
ReqAndReadyImplyGrant_A	412561653	118416734	0	0
ReqImpliesValid_A	412561653	124722535	0	0
ValidKnown_A	412561653	411800696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118416734	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118416734	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118416734	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	46745204	0	0
T1	335387	48501	0	0
T2	400434	530688	0	0
T3	3393	662	0	0
T4	48538	1344	0	0
T5	72914	2072	0	0
T6	1053	166	0	0
T8	45438	12963	0	0
T10	14232	256	0	0
T20	1100	128	0	0
T21	944	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	124722535	0	0
T1	335387	111803	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	11948	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118416734	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118416734	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	124722535	0	0
T1	335387	111803	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	11948	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T8,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T8,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T8,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T8,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412561653	411800696	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	412561653	118398609	0	0
GntImpliesValid_A	412561653	118398609	0	0
GrantKnown_A	412561653	411800696	0	0
IdxKnown_A	412561653	411800696	0	0
IndexIsCorrect_A	412561653	118398609	0	0
NoReadyValidNoGrant_A	412561653	46745205	0	0
Priority_A	412561653	124704409	0	0
ReadyAndValidImplyGrant_A	412561653	118398609	0	0
ReqAndReadyImplyGrant_A	412561653	118398609	0	0
ReqImpliesValid_A	412561653	124704409	0	0
ValidKnown_A	412561653	411800696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118398609	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118398609	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118398609	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	46745205	0	0
T1	335387	48501	0	0
T2	400434	530688	0	0
T3	3393	662	0	0
T4	48538	1344	0	0
T5	72914	2072	0	0
T6	1053	166	0	0
T8	45438	12963	0	0
T10	14232	256	0	0
T20	1100	128	0	0
T21	944	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	124704409	0	0
T1	335387	111803	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	11948	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118398609	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	118398609	0	0
T1	335387	93775	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	9641	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	124704409	0	0
T1	335387	111803	0	0
T2	400434	129428	0	0
T3	3393	175	0	0
T4	48538	14592	0	0
T5	72914	32351	0	0
T6	1053	46	0	0
T8	45438	11948	0	0
T10	14232	10204	0	0
T20	1100	32	0	0
T21	944	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T10,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T24
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T10,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8
1	1	Covered	T1,T2,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T24
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412561653	411800696	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	412561653	99035831	0	0
GntImpliesValid_A	412561653	99035831	0	0
GrantKnown_A	412561653	411800696	0	0
IdxKnown_A	412561653	411800696	0	0
IndexIsCorrect_A	412561653	99035831	0	0
NoReadyValidNoGrant_A	412561653	42264413	0	0
Priority_A	412561653	104972798	0	0
ReadyAndValidImplyGrant_A	412561653	99035831	0	0
ReqAndReadyImplyGrant_A	412561653	99035831	0	0
ReqImpliesValid_A	412561653	104972798	0	0
ValidKnown_A	412561653	411800696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	42264413	0	0
T1	335387	46659	0	0
T2	400434	524288	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	1807	0	0
T6	1053	0	0	0
T8	45438	15998	0	0
T9	0	220	0	0
T10	14232	635	0	0
T20	1100	0	0	0
T21	944	0	0	0
T24	0	37359	0	0
T44	0	42637	0	0
T45	0	34707	0	0
T84	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	104972798	0	0
T1	335387	150485	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	15413	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	15200	0	0
T44	0	16908	0	0
T84	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	104972798	0	0
T1	335387	150485	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	15413	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	15200	0	0
T44	0	16908	0	0
T84	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T10,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T10,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T24
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T10,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T8
1	1	Covered	T1,T2,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T24
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412561653	411800696	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	412561653	99035831	0	0
GntImpliesValid_A	412561653	99035831	0	0
GrantKnown_A	412561653	411800696	0	0
IdxKnown_A	412561653	411800696	0	0
IndexIsCorrect_A	412561653	99035831	0	0
NoReadyValidNoGrant_A	412561653	42264413	0	0
Priority_A	412561653	104972798	0	0
ReadyAndValidImplyGrant_A	412561653	99035831	0	0
ReqAndReadyImplyGrant_A	412561653	99035831	0	0
ReqImpliesValid_A	412561653	104972798	0	0
ValidKnown_A	412561653	411800696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	42264413	0	0
T1	335387	46659	0	0
T2	400434	524288	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	1807	0	0
T6	1053	0	0	0
T8	45438	15998	0	0
T9	0	220	0	0
T10	14232	635	0	0
T20	1100	0	0	0
T21	944	0	0	0
T24	0	37359	0	0
T44	0	42637	0	0
T45	0	34707	0	0
T84	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	104972798	0	0
T1	335387	150485	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	15413	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	15200	0	0
T44	0	16908	0	0
T84	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	99035831	0	0
T1	335387	134719	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	12206	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	14142	0	0
T44	0	15837	0	0
T84	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	104972798	0	0
T1	335387	150485	0	0
T2	400434	127897	0	0
T3	3393	0	0	0
T4	48538	0	0	0
T5	72914	23347	0	0
T6	1053	0	0	0
T8	45438	15413	0	0
T9	0	679	0	0
T10	14232	251	0	0
T20	1100	0	0	0
T21	944	0	0	0
T22	0	6369	0	0
T24	0	15200	0	0
T44	0	16908	0	0
T84	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412561653	411800696	0	0
T1	335387	335288	0	0
T2	400434	400418	0	0
T3	3393	2800	0	0
T4	48538	48470	0	0
T5	72914	72815	0	0
T6	1053	986	0	0
T8	45438	45375	0	0
T10	14232	14125	0	0
T20	1100	1017	0	0
T21	944	894	0	0