Line Coverage for Module :
prim_arbiter_tree_dup
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 9 | 90.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 0 | 0.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
ALWAYS | 139 | 3 | 3 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
0 |
1 |
132 |
1 |
1 |
137 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
146 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree_dup
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 132
EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T100,T157,T158 |
LINE 142
EXPRESSION (err_d | err_q)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T100,T157,T158 |
1 | 0 | Covered | T100,T157,T158 |
Branch Coverage for Module :
prim_arbiter_tree_dup
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
139 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 9 | 90.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 0 | 0.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
ALWAYS | 139 | 3 | 3 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
0 |
1 |
132 |
1 |
1 |
137 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
146 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 132
EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 142
EXPRESSION (err_d | err_q)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
139 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 9 | 90.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 0 | 0.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
ALWAYS | 139 | 3 | 3 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
0 |
1 |
132 |
1 |
1 |
137 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
146 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 132
EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T100,T157,T158 |
LINE 142
EXPRESSION (err_d | err_q)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T100,T157,T158 |
1 | 0 | Covered | T100,T157,T158 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
139 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |