SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_disable_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_disable_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.26 | 97.67 | 85.11 | 100.00 | u_eflash |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.87 | 100.00 | 91.51 | 100.00 | 97.83 | 100.00 | gen_flash_cores[0].u_core |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.36 | 100.00 | 83.96 | 100.00 | 97.83 | 100.00 | gen_flash_cores[1].u_core |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 8 | 8 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 4208 | 4208 | 0 | 0 |
OutputsKnown_A | 1650246612 | 1647202784 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1650246612 | 1647202784 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 4208 | 4208 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T5 | 4 | 4 | 0 | 0 |
T6 | 4 | 4 | 0 | 0 |
T8 | 4 | 4 | 0 | 0 |
T10 | 4 | 4 | 0 | 0 |
T20 | 4 | 4 | 0 | 0 |
T21 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1650246612 | 1647202784 | 0 | 0 |
T1 | 1341548 | 1341152 | 0 | 0 |
T2 | 1601736 | 1601672 | 0 | 0 |
T3 | 13572 | 11200 | 0 | 0 |
T4 | 194152 | 193880 | 0 | 0 |
T5 | 291656 | 291260 | 0 | 0 |
T6 | 4212 | 3944 | 0 | 0 |
T8 | 181752 | 181500 | 0 | 0 |
T10 | 56928 | 56500 | 0 | 0 |
T20 | 4400 | 4068 | 0 | 0 |
T21 | 3776 | 3576 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1650246612 | 1647202784 | 0 | 0 |
T1 | 1341548 | 1341152 | 0 | 0 |
T2 | 1601736 | 1601672 | 0 | 0 |
T3 | 13572 | 11200 | 0 | 0 |
T4 | 194152 | 193880 | 0 | 0 |
T5 | 291656 | 291260 | 0 | 0 |
T6 | 4212 | 3944 | 0 | 0 |
T8 | 181752 | 181500 | 0 | 0 |
T10 | 56928 | 56500 | 0 | 0 |
T20 | 4400 | 4068 | 0 | 0 |
T21 | 3776 | 3576 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 8 | 8 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 412561653 | 411800696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 412561653 | 411800696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 412561653 | 411800696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 412561653 | 411800696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 412561653 | 411800696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 412561653 | 411800696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 412561653 | 411800696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 412561653 | 411800696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 412561653 | 411800696 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 48538 | 48470 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 1100 | 1017 | 0 | 0 |
T21 | 944 | 894 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |