Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.36 97.14 92.91 98.44 100.00 98.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 97.36 97.14 92.91 98.44 100.00 98.33



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.36 97.14 92.91 98.44 100.00 98.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.38 95.85 94.18 98.95 92.52 98.49 98.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 99.65 100.00 100.00 98.95
u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_eflash 97.81 98.42 93.22 99.62 97.62 99.52 98.44
u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
u_flash_ctrl_rd 94.44 83.02 93.94 100.00 100.00 95.24
u_flash_hw_if 96.18 99.02 93.52 95.83 92.11 96.62 100.00
u_flash_mp 99.54 100.00 98.16 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 93.75 100.00 75.00 100.00 100.00
u_intr_prog_lvl 91.67 100.00 66.67 100.00 100.00
u_intr_rd_full 93.75 100.00 75.00 100.00 100.00
u_intr_rd_lvl 93.75 100.00 75.00 100.00 100.00
u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
u_prog_empty_event 100.00 100.00 100.00 100.00
u_prog_fifo 97.06 100.00 88.24 100.00 100.00
u_prog_lvl_event 88.89 100.00 66.67 100.00
u_prog_tl_gate 86.86 100.00 92.50 57.14 97.14 87.50
u_rd_full_event 100.00 100.00 100.00 100.00
u_rd_lvl_event 100.00 100.00 100.00 100.00
u_reg_core 99.37 99.12 98.56 100.00 99.18 100.00
u_reg_idle 100.00 100.00 100.00
u_region_cfg 87.91 63.73 100.00 100.00
u_sw_rd_fifo 92.86 95.24 85.29 90.91 100.00
u_tl_adapter_eflash 93.20 91.60 81.01 100.00 93.41 100.00
u_tl_gate 84.79 100.00 85.00 57.14 94.29 87.50
u_to_prog_fifo 79.40 89.33 64.86 82.14 81.25
u_to_rd_fifo 91.01 88.89 76.99 100.00 89.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
TOTAL14013697.14
CONT_ASSIGN41511100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42411100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN58011100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN62611100.00
CONT_ASSIGN63111100.00
ALWAYS63555100.00
CONT_ASSIGN67311100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN67511100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN73011100.00
ALWAYS75177100.00
CONT_ASSIGN78411100.00
CONT_ASSIGN78511100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN85911100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86211100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86511100.00
CONT_ASSIGN86611100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86911100.00
CONT_ASSIGN87211100.00
CONT_ASSIGN87511100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN880100.00
CONT_ASSIGN882100.00
CONT_ASSIGN88611100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88911100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN904100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90711100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN93711100.00
CONT_ASSIGN94211100.00
CONT_ASSIGN94511100.00
CONT_ASSIGN94811100.00
CONT_ASSIGN95011100.00
CONT_ASSIGN95811100.00
CONT_ASSIGN99811100.00
CONT_ASSIGN100211100.00
CONT_ASSIGN101411100.00
CONT_ASSIGN101511100.00
CONT_ASSIGN102911100.00
CONT_ASSIGN104311100.00
CONT_ASSIGN104411100.00
CONT_ASSIGN106211100.00
CONT_ASSIGN106311100.00
CONT_ASSIGN106411100.00
CONT_ASSIGN106511100.00
CONT_ASSIGN106611100.00
CONT_ASSIGN106711100.00
CONT_ASSIGN106811100.00
CONT_ASSIGN1069100.00
CONT_ASSIGN107011100.00
CONT_ASSIGN107111100.00
CONT_ASSIGN109211100.00
CONT_ASSIGN109311100.00
CONT_ASSIGN109411100.00
CONT_ASSIGN109511100.00
CONT_ASSIGN109611100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110111100.00
CONT_ASSIGN110211100.00
CONT_ASSIGN110311100.00
CONT_ASSIGN111511100.00
CONT_ASSIGN111711100.00
CONT_ASSIGN111811100.00
CONT_ASSIGN111911100.00
CONT_ASSIGN112011100.00
CONT_ASSIGN112111100.00
CONT_ASSIGN112211100.00
CONT_ASSIGN112311100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112811100.00
CONT_ASSIGN112811100.00
CONT_ASSIGN112911100.00
CONT_ASSIGN112911100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
CONT_ASSIGN113411100.00
ALWAYS114055100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN125711100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN129111100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN141811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
415 1 1
416 1 1
417 1 1
418 1 1
419 1 1
420 1 1
421 1 1
422 1 1
423 1 1
424 1 1
425 1 1
426 1 1
511 1 1
576 1 1
580 1 1
582 1 1
626 1 1
631 1 1
635 1 1
636 1 1
637 1 1
639 1 1
640 1 1
673 1 1
674 1 1
675 1 1
695 1 1
699 1 1
730 1 1
751 1 1
753 1 1
754 1 1
757 1 1
758 1 1
761 1 1
762 1 1
784 1 1
785 1 1
856 1 1
858 1 1
859 1 1
860 1 1
861 1 1
862 1 1
863 1 1
864 1 1
865 1 1
866 1 1
867 1 1
869 1 1
872 1 1
875 1 1
878 1 1
880 0 1
882 0 1
886 1 1
887 1 1
888 1 1
889 1 1
890 1 1
891 1 1
892 1 1
893 1 1
894 1 1
895 1 1
896 1 1
897 1 1
898 1 1
899 1 1
900 1 1
901 1 1
903 1 1
904 0 1
905 1 1
906 1 1
907 1 1
913 1 1
937 1 1
942 1 1
945 1 1
948 1 1
950 1 1
958 1 1
998 1 1
1002 1 1
1014 1 1
1015 1 1
1029 1 1
1043 1 1
1044 1 1
1062 1 1
1063 1 1
1064 1 1
1065 1 1
1066 1 1
1067 1 1
1068 1 1
1069 0 1
1070 1 1
1071 1 1
1092 1 1
1093 1 1
1094 1 1
1095 1 1
1096 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1101 1 1
1102 1 1
1103 1 1
1115 1 1
1117 1 1
1118 1 1
1119 1 1
1120 1 1
1121 1 1
1122 1 1
1123 1 1
1124 1 1
1128 2 2
1129 2 2
1133 2 2
1134 2 2
1140 1 1
1141 1 1
1142 1 1
1144 1 1
1145 1 1
1256 1 1
1257 1 1
1290 1 1
1291 1 1
1307 1 1
1418 1 1


Cond Coverage for Module : flash_ctrl
TotalCoveredPercent
Conditions14113192.91
Logical14113192.91
Non-Logical00
Event00

 LINE       341
 EXPRESSION (sw_wvalid & prog_op_valid)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT99,T187,T188
11CoveredT1,T4,T5

 LINE       423
 EXPRESSION (op_type == FlashOpRead)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       424
 EXPRESSION (op_type == FlashOpProgram)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       425
 EXPRESSION (op_type == FlashOpErase)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       426
 EXPRESSION (if_sel == SwSel)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       433
 EXPRESSION (((~sw_sel)) & rd_ctrl_wen)
             -----1-----   -----2-----
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       511
 EXPRESSION (op_start & prog_op)
             ----1---   ---2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       562
 EXPRESSION (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done)
             --------1--------   ----2---   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T4,T6
010CoveredT1,T2,T3
100Not Covered

 LINE       580
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgNormal] & reg2hw.prog_type_en.normal.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT168,T183,T184
11CoveredT1,T2,T3

 LINE       582
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgRepair] & reg2hw.prog_type_en.repair.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT183,T184,T189
11CoveredT1,T2,T3

 LINE       626
 EXPRESSION (reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead))
             -----------1----------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T10
11CoveredT1,T2,T4

 LINE       626
 SUB-EXPRESSION (reg2hw.control.op.q == FlashOpRead)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       639
 EXPRESSION (adapter_req & sw_rfifo_rvalid)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T8,T9
11CoveredT1,T4,T6

 LINE       652
 EXPRESSION (sw_rfifo_rvalid | rd_no_op_d)
             -------1-------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10CoveredT1,T4,T6

 LINE       652
 EXPRESSION (adapter_rvalid | rd_no_op_q)
             -------1------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10CoveredT1,T4,T6

 LINE       673
 EXPRESSION (sw_sel & rd_ctrl_wen)
             ---1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       699
 EXPRESSION (op_start & rd_op)
             ----1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       700
 EXPRESSION (sw_sel ? sw_rfifo_wready : lcmgr_rready)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       730
 EXPRESSION (op_start & erase_op)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT4,T10,T9
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       794
 EXPRESSION (rd_flash_ovfl | prog_flash_ovfl)
             ------1------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashErasePage))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT71,T108,T109
11CoveredT2,T3,T4

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashErasePage)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashEraseBank))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T10,T5
10CoveredT2,T3,T4
11CoveredT71,T108,T109

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashEraseBank)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T5

 LINE       867
 EXPRESSION (flash_phy_busy | ctrl_init_busy)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       869
 EXPRESSION (ctrl_initialized & ((~flash_phy_busy)))
             --------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT152,T153,T150
11CoveredT1,T2,T3

 LINE       875
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       913
 SUB-EXPRESSION (flash_phy_req.req & (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase))
                 --------1--------   -----------------------------------2----------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       913
 SUB-EXPRESSION (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)
                 ---------1--------   -----------2----------   -----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT71,T108,T109
010CoveredT2,T3,T10
100CoveredT1,T2,T4

 LINE       937
 EXPRESSION ((sw_ctrl_done & ((|sw_ctrl_err))) | flash_phy_rsp.macro_err | update_err)
             ----------------1----------------   -----------2-----------   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT1,T4,T5

 LINE       937
 SUB-EXPRESSION (sw_ctrl_done & ((|sw_ctrl_err)))
                 ------1-----   --------2-------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T6
11CoveredT1,T4,T5

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT34,T190,T115
10CoveredT1,T2,T3
11CoveredT34,T190,T115

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT34,T190,T115
10CoveredT1,T2,T3
11CoveredT34,T190,T115

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT34,T190,T115
10CoveredT1,T2,T3
11CoveredT34,T190,T115

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe)
                 ----------------1----------------   -----------------2----------------
-1--2-StatusTests
01CoveredT34,T190,T115
10CoveredT1,T2,T3
11CoveredT34,T190,T115

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT34,T190,T115
10CoveredT1,T2,T3
11CoveredT34,T190,T115

 LINE       1071
 EXPRESSION (sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | sw_ctrl_err.prog_err)
             ---------1--------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT12
010CoveredT61,T66,T67
100CoveredT1,T4,T5

 LINE       1115
 EXPRESSION (intg_err | eflash_cmd_intg_err | tl_gate_intg_err | tl_prog_gate_intg_err)
             ----1---   ---------2---------   --------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT17,T18,T19
0010CoveredT17,T18,T19
0100CoveredT31,T32,T33
1000CoveredT17,T18,T19

 LINE       1123
 EXPRESSION (rd_cnt_err | prog_cnt_err)
             -----1----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       1124
 EXPRESSION (flash_phy_rsp.fifo_err | adapter_fifo_err)
             -----------1----------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       1129
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T46,T47

 LINE       1129
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T46,T47

 LINE       1144
 EXPRESSION (sw_rfifo_wen & sw_rfifo_wready)
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       1145
 EXPRESSION (prog_fifo_rvalid & prog_fifo_ren)
             --------1-------   ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       1182
 EXPRESSION (prog_fifo_rd_q & (reg2hw.fifo_lvl.prog.q == 5'(prog_fifo_depth)))
             -------1------   -----------------------2-----------------------
-1--2-StatusTests
01CoveredT58,T59,T191
10CoveredT1,T2,T4
11CoveredT58,T59,T60

 LINE       1182
 SUB-EXPRESSION (reg2hw.fifo_lvl.prog.q == 5'(prog_fifo_depth))
                -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT58,T59,T191

 LINE       1234
 EXPRESSION (sw_rd_fifo_wr_q & (reg2hw.fifo_lvl.rd.q == sw_rfifo_depth))
             -------1-------   --------------------2-------------------
-1--2-StatusTests
01CoveredT4,T25,T24
10CoveredT1,T4,T6
11CoveredT4,T25,T24

 LINE       1234
 SUB-EXPRESSION (reg2hw.fifo_lvl.rd.q == sw_rfifo_depth)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T25,T24

 LINE       1418
 EXPRESSION (prog_op_valid | rd_op_valid | erase_op_valid)
             ------1------   -----2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT1,T2,T3
100CoveredT1,T2,T4

Toggle Coverage for Module : flash_ctrl
TotalCoveredPercent
Totals 122 111 90.98
Total Bits 2750 2707 98.44
Total Bits 0->1 1375 1354 98.47
Total Bits 1->0 1375 1353 98.40

Ports 122 111 90.98
Port Bits 2750 2707 98.44
Port Bits 0->1 1375 1354 98.47
Port Bits 1->0 1375 1353 98.40

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
rst_ni Yes Yes T48,T49,T50 Yes T16,T48,T49 INPUT
rst_shadowed_ni Yes Yes T48,T49,T50 Yes T16,T48,T49 INPUT
clk_otp_i Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
rst_otp_ni Yes Yes T48,T49,T50 Yes T16,T48,T49 INPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T54,T138,T139 Yes T16,T53,T54 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T16,T53,T54 Yes T16,T53,T54 INPUT
lc_iso_part_sw_rd_en_i[3:0] Yes Yes T53,T138,T139 Yes T16,T53,T54 INPUT
lc_iso_part_sw_wr_en_i[3:0] Yes Yes T53,T138,T139 Yes T16,T53,T54 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T23,T192,T193 Yes T23,T192,T193 INPUT
lc_escalate_en_i[0] No No Yes T6,T175,T176 INPUT
lc_escalate_en_i[1] No Yes *T6,*T28,*T174 No INPUT
lc_escalate_en_i[2] No No Yes T6,T28,T175 INPUT
lc_escalate_en_i[3] No Yes T28,T174,T176 No INPUT
lc_nvm_debug_en_i[3:0] Yes Yes T23,T192,T193 Yes T20,T21,T194 INPUT
core_tl_i.d_ready Yes Yes T48,T49,T51 Yes T16,T48,T49 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T48,T49,T51 Yes T48,T49,T51 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_i.a_mask[3:0] Yes Yes T16,T48,T49 Yes T48,T49,T51 INPUT
core_tl_i.a_address[31:0] Yes Yes T48,T49,T51 Yes T48,T49,T51 INPUT
core_tl_i.a_source[7:0] Yes Yes T48,T49,T51 Yes T48,T49,T51 INPUT
core_tl_i.a_size[1:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_i.a_valid Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
core_tl_o.a_ready Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
core_tl_o.d_error Yes Yes T16,T48,T49 Yes T48,T49,T53 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T16,T48,T49 Yes T48,T49,T53 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T48,T49,T53 Yes T48,T49,T51 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T16,*T48,*T49 Yes T16,T48,T49 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
prim_tl_i.d_ready Yes Yes T48,T49,T51 Yes T16,T48,T49 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T48,T49,T51 Yes T48,T49,T53 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T48,T49,T53 Yes T48,T49,T51 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T48,T49,T51 Yes T48,T49,T53 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T48,T49,T51 Yes T48,T49,T52 INPUT
prim_tl_i.a_address[31:0] Yes Yes T48,T49,T51 Yes T48,T49,T53 INPUT
prim_tl_i.a_source[7:0] Yes Yes T48,T49,T51 Yes T48,T49,T52 INPUT
prim_tl_i.a_size[1:0] Yes Yes T48,T49,T52 Yes T48,T49,T53 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T48,T49,T51 Yes T48,T49,T53 INPUT
prim_tl_i.a_valid Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
prim_tl_o.a_ready Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_error Yes Yes T48,T49,T195 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T48,T49,T195 Yes T48,T49,T195 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes T48,T49,*T53 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T48,T49,T195 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T48,*T49,*T53 Yes T48,T49,T53 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
mem_tl_i.d_ready Yes Yes T48,T51,T52 Yes T16,T48,T49 INPUT
mem_tl_i.a_user.data_intg[6:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_user.cmd_intg[6:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_user.instr_type[3:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_data[31:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_mask[3:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_address[31:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_source[7:0] Yes Yes T48,T49,T54 Yes T48,T49,T54 INPUT
mem_tl_i.a_size[1:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_opcode[2:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_i.a_valid Yes Yes T48,T49,T53 Yes T48,T49,T53 INPUT
mem_tl_o.a_ready Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
mem_tl_o.d_error Yes Yes T16,T48,T49 Yes T48,T49,T53 OUTPUT
mem_tl_o.d_user.data_intg[6:0] Yes Yes T1,T10,T7 Yes T1,T10,T7 OUTPUT
mem_tl_o.d_user.rsp_intg[5:0] Yes Yes T48,T49,T53 Yes T16,T48,T49 OUTPUT
mem_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_data[31:0] Yes Yes T49,T53,T54 Yes T49,T53,T54 OUTPUT
mem_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_source[7:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
mem_tl_o.d_size[1:0] Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
mem_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_opcode[0] Yes Yes *T48,*T49,*T53 Yes T48,T49,T53 OUTPUT
mem_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_valid Yes Yes T48,T49,T53 Yes T48,T49,T53 OUTPUT
otp_o.addr_req Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
otp_o.data_req Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
otp_i.seed_valid Yes Yes T16,T53,T54 Yes T16,T53,T54 INPUT
otp_i.rand_key[127:0] Yes Yes T16,T53,T54 Yes T16,T53,T54 INPUT
otp_i.key[127:0] Yes Yes T53,T196,T197 Yes T16,T53,T54 INPUT
otp_i.addr_ack Yes Yes T16,T53,T54 Yes T16,T53,T54 INPUT
otp_i.data_ack Yes Yes T16,T53,T54 Yes T16,T53,T54 INPUT
rma_req_i[3:0] Yes Yes T2,T3,T84 Yes T2,T3,T84 INPUT
rma_seed_i[31:0] Yes Yes T84,T164,T149 Yes T2,T3,T84 INPUT
rma_ack_o[3:0] Yes Yes T82,T198,T199 Yes T2,T84,T149 OUTPUT
pwrmgr_o.flash_idle Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][0] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][1] Yes Yes T4,T10,T84 Yes T4,T10,T84 OUTPUT
keymgr_o.seeds[0][2] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][3] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][4] Yes Yes T21,T84,T22 Yes T21,T84,T22 OUTPUT
keymgr_o.seeds[0][5] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][6] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][9:7] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][10] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][11] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][12] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[0][13] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][14] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][17:15] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][18] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][21:19] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][22] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][23] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][24] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][25] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][26] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][27] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][28] Yes Yes T2,T7,T9 Yes T2,T7,T9 OUTPUT
keymgr_o.seeds[0][32:29] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][33] Yes Yes T2,T84,T22 Yes T2,T84,T22 OUTPUT
keymgr_o.seeds[0][35:34] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][36] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][37] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][38] Yes Yes T2,T21,T85 Yes T2,T21,T85 OUTPUT
keymgr_o.seeds[0][40:39] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][41] Yes Yes T4,T10,T7 Yes T4,T10,T7 OUTPUT
keymgr_o.seeds[0][42] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[0][43] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[0][44] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][45] Yes Yes T7,T9,T22 Yes T7,T9,T22 OUTPUT
keymgr_o.seeds[0][46] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][47] Yes Yes T2,T10,T9 Yes T2,T10,T9 OUTPUT
keymgr_o.seeds[0][48] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][49] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][50] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][52:51] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][53] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][54] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[0][55] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][56] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][57] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][58] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[0][60:59] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][61] Yes Yes T2,T7,T9 Yes T2,T7,T9 OUTPUT
keymgr_o.seeds[0][62] Yes Yes T2,T85,T25 Yes T2,T85,T25 OUTPUT
keymgr_o.seeds[0][63] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][64] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[0][65] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][66] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][67] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][68] Yes Yes T2,T9,T22 Yes T2,T9,T22 OUTPUT
keymgr_o.seeds[0][69] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][70] Yes Yes T4,T10,T7 Yes T4,T10,T7 OUTPUT
keymgr_o.seeds[0][71] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][72] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][73] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][74] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][75] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][77:76] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][78] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][79] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][80] Yes Yes T2,T21,T9 Yes T2,T21,T9 OUTPUT
keymgr_o.seeds[0][81] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][82] Yes Yes T2,T4,T9 Yes T2,T4,T9 OUTPUT
keymgr_o.seeds[0][83] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][84] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][85] Yes Yes T10,T21,T84 Yes T10,T21,T84 OUTPUT
keymgr_o.seeds[0][86] Yes Yes T10,T84,T9 Yes T10,T84,T9 OUTPUT
keymgr_o.seeds[0][90:87] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][91] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][92] Yes Yes T10,T21,T84 Yes T10,T21,T84 OUTPUT
keymgr_o.seeds[0][98:93] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][99] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][101:100] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][102] Yes Yes T4,T21,T84 Yes T4,T21,T84 OUTPUT
keymgr_o.seeds[0][103] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][104] Yes Yes T2,T84,T22 Yes T2,T84,T22 OUTPUT
keymgr_o.seeds[0][105] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][106] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][107] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][108] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][109] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][115:110] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][116] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][117] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][118] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][119] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][120] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][121] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][123:122] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][124] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][125] Yes Yes T10,T7,T84 Yes T10,T7,T84 OUTPUT
keymgr_o.seeds[0][129:126] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][130] Yes Yes T10,T9,T22 Yes T10,T9,T22 OUTPUT
keymgr_o.seeds[0][131] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][132] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][133] Yes Yes T2,T10,T9 Yes T2,T10,T9 OUTPUT
keymgr_o.seeds[0][138:134] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][139] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][140] Yes Yes T10,T21,T84 Yes T10,T21,T84 OUTPUT
keymgr_o.seeds[0][142:141] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][143] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][147:144] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][148] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][150:149] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][151] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][152] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][154:153] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][155] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[0][156] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][157] Yes Yes T4,T10,T7 Yes T4,T10,T7 OUTPUT
keymgr_o.seeds[0][158] Yes Yes T2,T22,T85 Yes T2,T22,T85 OUTPUT
keymgr_o.seeds[0][159] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][160] Yes Yes T2,T9,T85 Yes T2,T9,T85 OUTPUT
keymgr_o.seeds[0][161] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][162] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][163] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][164] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][165] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][166] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[0][167] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][171:168] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][172] Yes Yes T10,T7,T84 Yes T10,T7,T84 OUTPUT
keymgr_o.seeds[0][173] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[0][174] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][175] Yes Yes T4,T7,T84 Yes T4,T7,T84 OUTPUT
keymgr_o.seeds[0][176] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][177] Yes Yes T10,T84,T22 Yes T10,T84,T22 OUTPUT
keymgr_o.seeds[0][178] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][179] Yes Yes T2,T84,T9 Yes T2,T84,T9 OUTPUT
keymgr_o.seeds[0][181:180] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][182] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][186:183] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][187] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][188] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][190:189] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][191] Yes Yes T4,T84,T9 Yes T4,T84,T9 OUTPUT
keymgr_o.seeds[0][192] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][193] Yes Yes T21,T84,T85 Yes T21,T84,T85 OUTPUT
keymgr_o.seeds[0][194] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][195] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][196] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][197] Yes Yes T2,T10,T84 Yes T2,T10,T84 OUTPUT
keymgr_o.seeds[0][198] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][200:199] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][201] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[0][202] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][203] Yes Yes T2,T21,T22 Yes T2,T21,T22 OUTPUT
keymgr_o.seeds[0][204] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][205] Yes Yes T2,T10,T9 Yes T2,T10,T9 OUTPUT
keymgr_o.seeds[0][207:206] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][208] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][211:209] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][212] Yes Yes T2,T10,T84 Yes T2,T10,T84 OUTPUT
keymgr_o.seeds[0][213] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][216:214] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][217] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[0][218] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][219] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][220] Yes Yes T2,T4,T9 Yes T2,T4,T9 OUTPUT
keymgr_o.seeds[0][221] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][222] Yes Yes T4,T10,T84 Yes T4,T10,T84 OUTPUT
keymgr_o.seeds[0][224:223] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][225] Yes Yes T4,T84,T85 Yes T4,T84,T85 OUTPUT
keymgr_o.seeds[0][228:226] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][229] Yes Yes T4,T21,T7 Yes T4,T21,T7 OUTPUT
keymgr_o.seeds[0][230] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][231] Yes Yes T2,T7,T9 Yes T2,T7,T9 OUTPUT
keymgr_o.seeds[0][232] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[0][233] Yes Yes T4,T10,T7 Yes T4,T10,T7 OUTPUT
keymgr_o.seeds[0][234] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[0][235] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][236] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][237] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[0][238] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[0][240:239] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][241] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[0][242] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][243] Yes Yes T2,T84,T9 Yes T2,T84,T9 OUTPUT
keymgr_o.seeds[0][244] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[0][245] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][246] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[0][247] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[0][249:248] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][250] Yes Yes T4,T7,T84 Yes T4,T7,T84 OUTPUT
keymgr_o.seeds[0][251] Yes Yes T21,T85,T200 Yes T21,T85,T200 OUTPUT
keymgr_o.seeds[0][252] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[0][254:253] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[0][255] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][0] Yes Yes T2,T10,T84 Yes T2,T10,T84 OUTPUT
keymgr_o.seeds[1][3:1] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][4] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][6:5] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][7] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][13:8] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][14] Yes Yes T7,T84,T9 Yes T7,T84,T9 OUTPUT
keymgr_o.seeds[1][19:15] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][20] Yes Yes T21,T7,T84 Yes T21,T7,T84 OUTPUT
keymgr_o.seeds[1][21] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][22] Yes Yes T21,T84,T22 Yes T21,T84,T22 OUTPUT
keymgr_o.seeds[1][23] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][24] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][25] Yes Yes T2,T4,T9 Yes T2,T4,T9 OUTPUT
keymgr_o.seeds[1][26] Yes Yes T10,T7,T84 Yes T10,T7,T84 OUTPUT
keymgr_o.seeds[1][28:27] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][29] Yes Yes T2,T10,T85 Yes T2,T10,T85 OUTPUT
keymgr_o.seeds[1][30] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][31] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[1][32] Yes Yes T7,T84,T9 Yes T7,T84,T9 OUTPUT
keymgr_o.seeds[1][34:33] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][35] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][36] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][37] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][44:38] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][45] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][46] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[1][47] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][48] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][49] Yes Yes T10,T21,T7 Yes T10,T21,T7 OUTPUT
keymgr_o.seeds[1][50] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[1][51] Yes Yes T10,T7,T84 Yes T10,T7,T84 OUTPUT
keymgr_o.seeds[1][52] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][53] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][54] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][55] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[1][57:56] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][58] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][59] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[1][61:60] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][62] Yes Yes T4,T7,T22 Yes T4,T7,T22 OUTPUT
keymgr_o.seeds[1][63] Yes Yes T2,T84,T9 Yes T2,T84,T9 OUTPUT
keymgr_o.seeds[1][64] Yes Yes T2,T10,T22 Yes T2,T10,T22 OUTPUT
keymgr_o.seeds[1][65] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][66] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][67] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][68] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][69] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[1][70] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][71] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[1][72] Yes Yes T9,T85,T200 Yes T9,T85,T200 OUTPUT
keymgr_o.seeds[1][73] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][74] Yes Yes T21,T84,T22 Yes T21,T84,T22 OUTPUT
keymgr_o.seeds[1][75] Yes Yes T2,T7,T85 Yes T2,T7,T85 OUTPUT
keymgr_o.seeds[1][76] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][77] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[1][78] Yes Yes T2,T4,T9 Yes T2,T4,T9 OUTPUT
keymgr_o.seeds[1][79] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[1][80] Yes Yes T2,T4,T85 Yes T2,T4,T85 OUTPUT
keymgr_o.seeds[1][81] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][82] Yes Yes T2,T7,T9 Yes T2,T7,T9 OUTPUT
keymgr_o.seeds[1][83] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][84] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][87:85] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][88] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[1][89] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][91:90] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][92] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][93] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][94] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][95] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][96] Yes Yes T4,T21,T7 Yes T4,T21,T7 OUTPUT
keymgr_o.seeds[1][97] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[1][98] Yes Yes T2,T21,T22 Yes T2,T21,T22 OUTPUT
keymgr_o.seeds[1][99] Yes Yes T10,T21,T7 Yes T10,T21,T7 OUTPUT
keymgr_o.seeds[1][100] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][101] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][102] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][103] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][104] Yes Yes T4,T10,T84 Yes T4,T10,T84 OUTPUT
keymgr_o.seeds[1][106:105] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][107] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][110:108] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][111] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[1][114:112] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][115] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][116] Yes Yes T21,T84,T9 Yes T21,T84,T9 OUTPUT
keymgr_o.seeds[1][120:117] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][121] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[1][124:122] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][125] Yes Yes T2,T21,T84 Yes T2,T21,T84 OUTPUT
keymgr_o.seeds[1][126] Yes Yes T4,T21,T7 Yes T4,T21,T7 OUTPUT
keymgr_o.seeds[1][129:127] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][130] Yes Yes T2,T84,T9 Yes T2,T84,T9 OUTPUT
keymgr_o.seeds[1][131] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][132] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][133] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][136:134] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][137] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][138] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][139] Yes Yes T2,T10,T84 Yes T2,T10,T84 OUTPUT
keymgr_o.seeds[1][142:140] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][143] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][144] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][145] Yes Yes T4,T84,T22 Yes T4,T84,T22 OUTPUT
keymgr_o.seeds[1][148:146] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][149] Yes Yes T21,T22,T85 Yes T21,T22,T85 OUTPUT
keymgr_o.seeds[1][152:150] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][153] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][154] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][155] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][156] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[1][157] Yes Yes T4,T21,T7 Yes T4,T21,T7 OUTPUT
keymgr_o.seeds[1][158] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][159] Yes Yes T21,T7,T84 Yes T21,T7,T84 OUTPUT
keymgr_o.seeds[1][160] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][161] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][162] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][163] Yes Yes T21,T84,T9 Yes T21,T84,T9 OUTPUT
keymgr_o.seeds[1][169:164] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][170] Yes Yes T84,T85,T200 Yes T84,T85,T200 OUTPUT
keymgr_o.seeds[1][172:171] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][173] Yes Yes T2,T84,T9 Yes T2,T84,T9 OUTPUT
keymgr_o.seeds[1][175:174] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][176] Yes Yes T10,T7,T84 Yes T10,T7,T84 OUTPUT
keymgr_o.seeds[1][177] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][178] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][179] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][181:180] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][182] Yes Yes T21,T84,T9 Yes T21,T84,T9 OUTPUT
keymgr_o.seeds[1][183] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][184] Yes Yes T21,T7,T84 Yes T21,T7,T84 OUTPUT
keymgr_o.seeds[1][185] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][186] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
keymgr_o.seeds[1][187] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][188] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][189] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][190] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][191] Yes Yes T4,T21,T84 Yes T4,T21,T84 OUTPUT
keymgr_o.seeds[1][192] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][193] Yes Yes T84,T9,T85 Yes T84,T9,T85 OUTPUT
keymgr_o.seeds[1][194] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[1][195] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][196] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][202:197] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][203] Yes Yes T4,T7,T84 Yes T4,T7,T84 OUTPUT
keymgr_o.seeds[1][205:204] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][206] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][208:207] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][209] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[1][210] Yes Yes T4,T84,T85 Yes T4,T84,T85 OUTPUT
keymgr_o.seeds[1][211] Yes Yes T4,T10,T21 Yes T4,T10,T21 OUTPUT
keymgr_o.seeds[1][212] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][214:213] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][215] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][216] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[1][217] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][218] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[1][219] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][225:220] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][226] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][227] Yes Yes T2,T7,T84 Yes T2,T7,T84 OUTPUT
keymgr_o.seeds[1][229:228] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][230] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][231] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][232] Yes Yes T21,T7,T22 Yes T21,T7,T22 OUTPUT
keymgr_o.seeds[1][233] Yes Yes T10,T21,T23 Yes T10,T21,T23 OUTPUT
keymgr_o.seeds[1][234] Yes Yes T2,T10,T7 Yes T2,T10,T7 OUTPUT
keymgr_o.seeds[1][238:235] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][239] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][242:240] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][243] Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
keymgr_o.seeds[1][244] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][245] Yes Yes T10,T21,T7 Yes T10,T21,T7 OUTPUT
keymgr_o.seeds[1][247:246] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][248] Yes Yes T2,T10,T21 Yes T2,T10,T21 OUTPUT
keymgr_o.seeds[1][249] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][250] Yes Yes T2,T21,T7 Yes T2,T21,T7 OUTPUT
keymgr_o.seeds[1][251] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
keymgr_o.seeds[1][252] Yes Yes T2,T4,T10 Yes T2,T4,T10 OUTPUT
keymgr_o.seeds[1][253] Yes Yes T2,T4,T84 Yes T2,T4,T84 OUTPUT
keymgr_o.seeds[1][255:254] Yes Yes T16,T53,T54 Yes T16,T53,T54 OUTPUT
cio_tck_i No No No INPUT
cio_tms_i No No No INPUT
cio_tdi_i No No No INPUT
cio_tdo_en_o No No No OUTPUT
cio_tdo_o No No Yes T20,T21,T194 OUTPUT
intr_corr_err_o Yes Yes T197,T201,T202 Yes T197,T201,T202 OUTPUT
intr_prog_empty_o Yes Yes T197,T201,T202 Yes T197,T201,T202 OUTPUT
intr_prog_lvl_o Yes Yes T197,T203,T202 Yes T197,T203,T202 OUTPUT
intr_rd_full_o Yes Yes T201,T202,T204 Yes T201,T202,T204 OUTPUT
intr_rd_lvl_o Yes Yes T201,T202,T205 Yes T201,T202,T205 OUTPUT
intr_op_done_o Yes Yes T197,T203,T202 Yes T197,T203,T202 OUTPUT
alert_rx_i[0].ack_n Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
alert_rx_i[0].ack_p Yes Yes T48,T49,T50 Yes T48,T49,T50 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
alert_rx_i[1].ack_p Yes Yes T48,T49,T50 Yes T48,T49,T50 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
alert_rx_i[2].ack_p Yes Yes T48,T49,T50 Yes T48,T49,T50 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
alert_rx_i[3].ack_p Yes Yes T48,T50,T195 Yes T48,T50,T195 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T16,T48,T49 Yes T16,T48,T49 INPUT
alert_rx_i[4].ack_p Yes Yes T48,T49,T50 Yes T48,T49,T50 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
alert_tx_o[0].alert_p Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
alert_tx_o[1].alert_n Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
alert_tx_o[1].alert_p Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
alert_tx_o[2].alert_n Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
alert_tx_o[2].alert_p Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
alert_tx_o[3].alert_n Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
alert_tx_o[3].alert_p Yes Yes T48,T50,T195 Yes T48,T50,T195 OUTPUT
alert_tx_o[4].alert_n Yes Yes T16,T48,T49 Yes T16,T48,T49 OUTPUT
alert_tx_o[4].alert_p Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
fla_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T16,T48,T49 Yes T48,T49,T50 INPUT
flash_power_ready_h_i Yes Yes T152,T153,T150 Yes T152,T153,T150 INPUT
flash_test_mode_a_io[1:0] No No No INOUT
flash_test_voltage_h_io No No No INOUT

*Tests covering at least one bit in the range

Branch Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
Branches 16 16 100.00
TERNARY 875 2 2 100.00
TERNARY 1129 2 2 100.00
TERNARY 1129 2 2 100.00
TERNARY 700 2 2 100.00
IF 635 2 2 100.00
CASE 751 4 4 100.00
IF 1140 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 875 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1129 ((®2hw.ecc_single_err_cnt[0].q)) ?

Branches:
-1-StatusTests
1 Covered T1,T46,T47
0 Covered T1,T2,T3


LineNo. Expression -1-: 1129 ((®2hw.ecc_single_err_cnt[1].q)) ?

Branches:
-1-StatusTests
1 Covered T1,T46,T47
0 Covered T1,T2,T3


LineNo. Expression -1-: 700 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 635 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 751 case (op_type)

Branches:
-1-StatusTests
FlashOpRead Covered T1,T2,T3
FlashOpProgram Covered T1,T2,T4
FlashOpErase Covered T2,T3,T4
default Covered T1,T2,T3


LineNo. Expression -1-: 1140 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 60 60 100.00 59 98.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 60 60 100.00 59 98.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FifoDepthCheck_A 1052 1052 0 0
FlashAddrKnown_A 412561653 294268849 0 0
FlashAddrKnown_AKnownEnable 412561653 411800696 0 0
FlashKnownO_A 412561653 411800696 0 0
FlashProgKnown_A 412561653 177637815 0 0
FlashProgKnown_AKnownEnable 412561653 411800696 0 0
FpvSecCmAddrCntAlertCheck_A 412561653 50 0 0
FpvSecCmArbFsmCheck_A 412561653 50 0 0
FpvSecCmLcCtrlFsmCheck_A 412561653 50 0 0
FpvSecCmLcCtrlRmaFsmCheck_A 412561653 50 0 0
FpvSecCmPageCntAlertCheck_A 412561653 50 0 0
FpvSecCmProgCnt_A 412561653 50 0 0
FpvSecCmRdCnt_A 412561653 50 0 0
FpvSecCmRdFifoRptrCheck_A 412561653 50 0 0
FpvSecCmRdFifoWptrCheck_A 412561653 50 0 0
FpvSecCmRegWeOnehotCheck_A 412561653 50 0 0
FpvSecCmSeedCntAlertCheck_A 412561653 50 0 0
FpvSecCmTlLcGateFsm_A 412561653 50 0 0
FpvSecCmTlProgLcGateFsm_A 412561653 50 0 0
FpvSecCmWipeIdx_A 412561653 50 0 0
FpvSecCmWordCntAlertCheck_A 412561653 50 0 0
IntrErrO_A 412561653 411800696 0 0
IntrOpDoneKnownO_A 412561653 411800696 0 0
IntrProgEmptyKnownO_A 412561653 411800696 0 0
IntrProgLvlKnownO_A 412561653 411800696 0 0
IntrProgRdFullKnownO_A 412561653 411800696 0 0
IntrRdLvlKnownO_A 412561653 411800696 0 0
MemRspPayLoad_A 412561653 4867767 0 0
MemRspPayLoad_AKnownEnable 412561653 411800696 0 0
MemTlAReadyKnownO_A 412561653 411800696 0 0
MemTlDValidKnownO_A 412561653 411800696 0 0
PrimRspPayLoad_A 412561653 0 0 0
PrimRspPayLoad_AKnownEnable 412561653 411800696 0 0
PrimTlAReadyKnownO_A 412561653 411800696 0 0
PrimTlDValidKnownO_A 412561653 411800696 0 0
RspPayLoad_A 412353993 36289676 0 0
RspPayLoad_AKnownEnable 412561653 411800696 0 0
TdoEnIsOne_A 412561653 411800696 0 0
TdoKnown_A 412561653 411800696 0 0
TlAReadyKnownO_A 412561653 411800696 0 0
TlDValidKnownO_A 412561653 411800696 0 0
gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 412561653 50 0 0
gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 412561653 50 0 0
gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 412561653 50 0 0
gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 412561653 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 412561653 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 412561653 15 0 0


FifoDepthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

FlashAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 294268849 0 0
T1 335387 283189 0 0
T2 400434 362824 0 0
T3 3393 838 0 0
T4 48538 15936 0 0
T5 72914 59577 0 0
T6 1053 212 0 0
T8 45438 31025 0 0
T10 14232 11283 0 0
T20 1100 160 0 0
T21 944 160 0 0

FlashAddrKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

FlashKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

FlashProgKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 177637815 0 0
T1 335387 245430 0 0
T2 400434 217536 0 0
T3 3393 0 0 0
T4 48538 14048 0 0
T5 72914 54177 0 0
T6 1053 0 0 0
T8 45438 0 0 0
T9 0 2089 0 0
T10 14232 0 0 0
T20 1100 0 0 0
T21 944 0 0 0
T22 0 12360 0 0
T23 0 32958 0 0
T25 0 13600 0 0
T45 0 270507 0 0
T84 0 217536 0 0

FlashProgKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

FpvSecCmAddrCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmArbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmLcCtrlFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmLcCtrlRmaFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmPageCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmProgCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmRdCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmRdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmRdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmSeedCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmTlProgLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmWipeIdx_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

FpvSecCmWordCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

IntrErrO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

IntrOpDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

IntrProgEmptyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

IntrProgLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

IntrProgRdFullKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

IntrRdLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

MemRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4867767 0 0
T1 335387 41367 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 2 0 0
T7 0 10 0 0
T8 45438 16489 0 0
T9 0 229 0 0
T10 14232 15 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 16723 0 0
T44 0 16862 0 0
T45 0 41733 0 0
T46 0 41762 0 0

MemRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

MemTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

MemTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

PrimRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 0 0 0

PrimRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

PrimTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

PrimTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 36289676 0 0
T1 335387 161539 0 0
T2 400434 1428 0 0
T3 3393 507 0 0
T4 48538 20621 0 0
T5 72914 35960 0 0
T6 1053 143 0 0
T8 45438 17191 0 0
T10 14232 6208 0 0
T20 1100 17 0 0
T21 944 58 0 0

RspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TdoEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 50 0 0
T17 102045 10 0 0
T18 151390 10 0 0
T19 195388 10 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 10 0 0
T207 0 10 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 15 0 0
T17 102045 1 0 0
T18 151390 1 0 0
T19 195388 5 0 0
T165 3509 0 0 0
T172 959 0 0 0
T206 0 5 0 0
T207 0 3 0 0
T208 2863 0 0 0
T209 2731 0 0 0
T210 1982 0 0 0
T211 727857 0 0 0
T212 2621 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%