Module Definition
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Module Instance : tb.dut.u_ctrl_arb.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_ctrl_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.75 100.00 92.71 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_rma_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.75 100.00 92.71 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.37 100.00 88.89 57.14 95.83 50.00 u_prog_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.60 100.00 100.00 57.14 95.83 50.00 u_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.87 100.00 91.51 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.68 100.00 98.41 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 83.96 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.37 100.00 96.83 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 9468 9468 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9468 9468 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T4 9 9 0 0
T5 9 9 0 0
T6 9 9 0 0
T8 9 9 0 0
T10 9 9 0 0
T20 9 9 0 0
T21 9 9 0 0

Line Coverage for Instance : tb.dut.u_ctrl_arb.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_ctrl_arb.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_rma_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_rma_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_gate.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_tl_gate.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
43 1 1
47 1 1
48 1 1
49 1 1
51 1 1


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1052 1052 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

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