Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_lcmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.75 100.00 92.71 92.11 98.94 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if 96.75 100.00 92.71 92.11 98.94 100.00



Module Instance : tb.dut.u_flash_hw_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.75 100.00 92.71 92.11 98.94 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.18 99.02 93.52 95.83 92.11 96.62 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_cnt 100.00 100.00
u_addr_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_bus_intg 100.00 100.00
u_data_intg_chk 100.00 100.00 100.00
u_data_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_page_cnt 78.79 78.79
u_prim_flop_err_sts 100.00 100.00 100.00
u_rma_state_regs 100.00 100.00 100.00 100.00
u_seed_cnt 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_sync_flash_init 100.00 100.00 100.00
u_sync_rma_req 100.00 100.00 100.00 100.00
u_wipe_idx_cnt 100.00 100.00
u_word_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
TOTAL242242100.00
CONT_ASSIGN14911100.00
ALWAYS15233100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
ALWAYS17477100.00
CONT_ASSIGN18511100.00
ALWAYS22555100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24511100.00
ALWAYS24933100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
ALWAYS26266100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
ALWAYS35799100.00
CONT_ASSIGN37811100.00
ALWAYS3848585100.00
CONT_ASSIGN60511100.00
ALWAYS61133100.00
ALWAYS66877100.00
ALWAYS6831010100.00
ALWAYS70022100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN73211100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN74911100.00
ALWAYS7566666100.00
CONT_ASSIGN88611100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88900
CONT_ASSIGN89000
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90411100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91611100.00
ALWAYS92700
CONT_ASSIGN93411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
149 1 1
152 3 3
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
177 1 1
179 1 1
180 1 1
181 1 1
185 1 1
225 1 1
226 1 1
227 1 1
229 1 1
230 1 1
241 1 1
245 1 1
249 1 1
250 1 1
252 1 1
259 1 1
260 1 1
262 1 1
263 1 1
264 1 1
266 1 1
268 1 1
269 1 1
MISSING_ELSE
276 1 1
277 1 1
278 1 1
357 1 1
358 1 1
359 1 1
361 1 1
362 1 1
363 1 1
MISSING_ELSE
366 1 1
367 1 1
368 1 1
MISSING_ELSE
378 1 1
384 1 1
387 1 1
388 1 1
389 1 1
390 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
400 1 1
402 1 1
403 1 1
404 1 1
407 1 1
409 1 1
410 1 1
413 1 1
414 1 1
417 1 1
418 1 1
421 1 1
423 1 1
425 1 1
431 1 1
432 1 1
433 1 1
434 1 1
MISSING_ELSE
439 1 1
440 1 1
441 1 1
442 1 1
443 1 1
444 1 1
MISSING_ELSE
449 1 1
450 1 1
451 1 1
452 1 1
453 1 1
455 1 1
MISSING_ELSE
462 1 1
465 1 1
466 1 1
467 1 1
470 1 1
471 1 1
472 1 1
473 1 1
474 1 1
475 1 1
476 1 1
MISSING_ELSE
481 1 1
482 1 1
483 1 1
485 1 1
486 1 1
487 1 1
489 1 1
495 1 1
496 1 1
497 1 1
MISSING_ELSE
503 1 1
504 1 1
505 1 1
==> MISSING_ELSE
510 1 1
511 1 1
512 1 1
514 1 1
518 1 1
519 1 1
520 1 1
MISSING_ELSE
529 1 1
530 1 1
531 1 1
532 1 1
534 1 1
541 1 1
542 1 1
543 1 1
547 1 1
548 1 1
549 1 1
550 1 1
567 1 1
570 1 1
MISSING_ELSE
605 1 1
611 3 3
668 1 1
669 1 1
670 1 1
671 1 1
673 1 1
674 1 1
675 1 1
683 1 1
684 1 1
685 1 1
686 1 1
687 1 1
688 1 1
689 1 1
MISSING_ELSE
691 1 1
692 1 1
693 1 1
MISSING_ELSE
MISSING_ELSE
700 1 1
701 1 1
MISSING_ELSE
709 1 1
710 1 1
732 1 1
736 1 1
737 1 1
749 1 1
756 1 1
757 1 1
758 1 1
759 1 1
760 1 1
761 1 1
762 1 1
763 1 1
764 1 1
765 1 1
766 1 1
767 1 1
768 1 1
769 1 1
770 1 1
772 1 1
779 1 1
780 1 1
781 1 1
782 1 1
783 1 1
MISSING_ELSE
788 1 1
789 1 1
790 1 1
791 1 1
793 1 1
794 1 1
795 1 1
800 1 1
801 1 1
802 1 1
803 1 1
804 1 1
MISSING_ELSE
809 1 1
810 1 1
814 1 1
815 1 1
816 1 1
817 1 1
819 1 1
820 1 1
821 1 1
826 1 1
827 1 1
828 1 1
830 1 1
831 1 1
MISSING_ELSE
836 1 1
837 1 1
839 1 1
840 1 1
841 1 1
842 1 1
MISSING_ELSE
847 1 1
848 1 1
849 1 1
851 1 1
852 1 1
853 1 1
854 1 1
MISSING_ELSE
857 1 1
858 1 1
MISSING_ELSE
863 1 1
867 1 1
868 1 1
869 1 1
886 1 1
887 1 1
888 1 1
889 unreachable
890 unreachable
891 1 1
892 1 1
893 1 1
895 1 1
897 1 1
900 1 1
901 1 1
903 1 1
904 1 1
906 1 1
909 1 1
913 1 1
916 1 1
927 unreachable
928 unreachable
==> MISSING_ELSE
934 1 1


Cond Coverage for Module : flash_ctrl_lcmgr
TotalCoveredPercent
Conditions968992.71
Logical968992.71
Non-Logical00
Event00

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T84

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT159,T160,T161
10Not Covered

 LINE       229
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       230
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       245
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T162,T163
10CoveredT35,T162,T163

 LINE       245
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------
-1--2-StatusTests
01CoveredT35,T162,T163
10CoveredT1,T2,T3
11CoveredT35,T162,T163

 LINE       264
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       268
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---
-1--2-StatusTests
01CoveredT2,T84,T149
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       361
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT75,T76,T77
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       366
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT3,T73,T74
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       455
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------
-1-StatusTests
0CoveredT164,T77,T165
1CoveredT1,T2,T3

 LINE       471
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       514
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------
-1--2-StatusTests
01CoveredT2,T84,T149
10CoveredT2,T84,T149
11CoveredT2,T84,T149

 LINE       514
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------
-1-StatusTests
0CoveredT2,T3,T84
1CoveredT2,T84,T149

 LINE       673
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       674
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       675
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT17,T18,T19

 LINE       688
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT166,T167
11CoveredT2,T84,T149

 LINE       692
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT2,T84,T149
10Unreachable
11CoveredT2,T84,T149

 LINE       700
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT166,T167
111CoveredT2,T84,T149

 LINE       830
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---
-1--2-StatusTests
01CoveredT2,T84,T149
10Not Covered
11CoveredT2,T84,T149

 LINE       830
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT2,T84,T149
1CoveredT2,T84,T149

 LINE       851
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT2,T84,T149
11CoveredT2,T84,T149

 LINE       851
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT2,T84,T149
1CoveredT2,T84,T149

 LINE       857
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT2,T84,T149
10Unreachable
11CoveredT2,T84,T149

 LINE       858
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT2,T84,T149
1CoveredT168,T78,T169

 LINE       887
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       888
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       891
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       892
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       895
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       901
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T84
10CoveredT1,T2,T3

 LINE       909
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------
-1--2--3--4--5--6--7-StatusTests
0000000CoveredT1,T2,T3
0000001CoveredT17,T18,T19
0000010CoveredT17,T18,T19
0000100CoveredT17,T18,T19
0001000CoveredT17,T18,T19
0010000CoveredT17,T18,T19
0100000CoveredT17,T18,T19
1000000CoveredT17,T18,T19

FSM Coverage for Module : flash_ctrl_lcmgr
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 25 23 92.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisabled 543 Covered T16
StEntropyReseed 497 Covered T16
StIdle 430 Covered T16
StInvalid 518 Covered T16
StReadEval 476 Covered T16
StReadSeeds 455 Covered T16
StReqAddrKey 434 Covered T16
StReqDataKey 444 Covered T16
StRmaRsp 518 Covered T16
StRmaWipe 432 Covered T16
StWait 455 Covered T16


transitionsLine No.CoveredTests
StEntropyReseed->StDisabled 570 Covered T16
StEntropyReseed->StRmaWipe 505 Covered T16
StIdle->StDisabled 570 Covered T16
StIdle->StReqAddrKey 434 Covered T16
StIdle->StRmaWipe 432 Covered T16
StInvalid->StDisabled 570 Not Covered
StReadEval->StDisabled 570 Covered T16
StReadEval->StReadSeeds 483 Covered T16
StReadSeeds->StDisabled 570 Covered T16
StReadSeeds->StReadEval 476 Covered T16
StReadSeeds->StWait 473 Covered T16
StReqAddrKey->StDisabled 570 Covered T16
StReqAddrKey->StReqDataKey 444 Covered T16
StReqAddrKey->StRmaWipe 442 Covered T16
StReqDataKey->StDisabled 570 Covered T16
StReqDataKey->StReadSeeds 455 Covered T16
StReqDataKey->StRmaWipe 452 Covered T16
StReqDataKey->StWait 455 Covered T16
StRmaRsp->StDisabled 570 Covered T16
StRmaRsp->StInvalid 532 Not Covered
StRmaWipe->StDisabled 570 Covered T16
StRmaWipe->StInvalid 518 Covered T16
StRmaWipe->StRmaRsp 518 Covered T16
StWait->StDisabled 570 Covered T16
StWait->StEntropyReseed 497 Covered T16


Summary for FSM :: rma_state_q
TotalCoveredPercent
States 10 10 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: rma_state_q
statesLine No.CoveredTests
StRmaDisabled 780 Covered T16
StRmaErase 791 Covered T16
StRmaEraseWait 804 Covered T16
StRmaIdle 795 Covered T16
StRmaInvalid 867 Covered T16
StRmaPageSel 782 Covered T16
StRmaProgram 817 Covered T16
StRmaProgramWait 831 Covered T16
StRmaRdVerify 842 Covered T16
StRmaWordSel 810 Covered T16


transitionsLine No.CoveredTests
StRmaErase->StRmaEraseWait 804 Covered T16
StRmaEraseWait->StRmaWordSel 810 Covered T16
StRmaIdle->StRmaDisabled 780 Covered T16
StRmaIdle->StRmaPageSel 782 Covered T16
StRmaPageSel->StRmaDisabled 789 Not Covered
StRmaPageSel->StRmaErase 791 Covered T16
StRmaPageSel->StRmaIdle 795 Covered T16
StRmaProgram->StRmaProgramWait 831 Covered T16
StRmaProgramWait->StRmaRdVerify 842 Covered T16
StRmaRdVerify->StRmaWordSel 854 Covered T16
StRmaWordSel->StRmaDisabled 815 Covered T16
StRmaWordSel->StRmaPageSel 821 Covered T16
StRmaWordSel->StRmaProgram 817 Covered T16



Branch Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
Branches 94 93 98.94
TERNARY 887 2 2 100.00
TERNARY 888 2 2 100.00
TERNARY 891 2 2 100.00
TERNARY 892 2 2 100.00
TERNARY 893 2 2 100.00
TERNARY 895 2 2 100.00
IF 152 2 2 100.00
IF 174 2 2 100.00
IF 225 2 2 100.00
IF 249 2 2 100.00
IF 262 4 4 100.00
IF 357 5 5 100.00
CASE 425 27 26 96.30
IF 567 2 2 100.00
IF 611 2 2 100.00
IF 668 2 2 100.00
IF 683 7 7 100.00
IF 700 2 2 100.00
CASE 772 23 23 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 887 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 888 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 891 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 892 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 893 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 895 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 174 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 225 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 249 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if ((!rst_ni)) -2-: 264 if (((seed_phase && validate_q) && rvalid_i)) -3-: 268 if ((seed_phase && rvalid_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 357 if ((!rst_ni)) -2-: 361 if ((addr_key_req_d && addr_key_ack_q)) -3-: 366 if ((data_key_req_d && data_key_ack_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 425 case (state_q) -2-: 431 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit])) -3-: 433 if (init_q) -4-: 441 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -5-: 443 if (addr_key_ack_q) -6-: 451 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -7-: 453 if (data_key_ack_q) -8-: 455 (provision_en_i) ? -9-: 471 if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds)) -10-: 474 if (done_i) -11-: 485 if (validate_q) -12-: 496 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait])) -13-: 504 if (edn_ack_i) -14-: 514 if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)) -15-: 519 if (rma_wipe_done) -16-: 531 if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
StIdle 1 - - - - - - - - - - - - - - Covered T101,T170,T168
StIdle 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 1 - - - - - - - - - - - - Covered T75,T77,T125
StReqAddrKey - - 0 1 - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 0 0 - - - - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 1 - - - - - - - - - - Covered T3,T74,T124
StReqDataKey - - - - 0 1 1 - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 0 1 0 - - - - - - - - Covered T164,T77,T165
StReqDataKey - - - - 0 0 - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 1 - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 1 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 0 - - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 1 - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 0 - - - - - Covered T1,T2,T3
StWait - - - - - - - - - - 1 - - - - Covered T2,T3,T84
StWait - - - - - - - - - - 0 - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - - - 1 - - - Covered T2,T3,T84
StEntropyReseed - - - - - - - - - - - 0 - - - Not Covered
StRmaWipe - - - - - - - - - - - - 1 - - Covered T2,T84,T149
StRmaWipe - - - - - - - - - - - - 0 1 - Covered T2,T84,T149
StRmaWipe - - - - - - - - - - - - 0 0 - Covered T2,T3,T84
StRmaRsp - - - - - - - - - - - - - - 1 Covered T14,T15
StRmaRsp - - - - - - - - - - - - - - 0 Covered T2,T84,T149
StDisabled - - - - - - - - - - - - - - - Covered T2,T3,T6
StInvalid - - - - - - - - - - - - - - - Covered T17,T18,T19
default - - - - - - - - - - - - - - - Covered T17,T18,T19


LineNo. Expression -1-: 567 if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 611 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 668 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 683 if ((!rst_ni)) -2-: 685 if (beat_cnt_clr) -3-: 687 if (prog_cnt_en) -4-: 688 if ((wvalid_o && wready_i)) -5-: 691 if (rd_cnt_en) -6-: 692 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T2,T84,T149
0 0 1 1 - - Covered T2,T84,T149
0 0 1 0 - - Covered T166,T14,T15
0 0 0 - 1 1 Covered T2,T84,T149
0 0 0 - 1 0 Covered T2,T84,T149
0 0 0 - 0 - Covered T1,T2,T3


LineNo. Expression -1-: 700 if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:
-1-StatusTests
1 Covered T2,T84,T149
0 Covered T1,T2,T3


LineNo. Expression -1-: 772 case (rma_state_q) -2-: 779 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -3-: 781 if (rma_wipe_req_int) -4-: 788 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -5-: 790 if ((page_cnt < end_page)) -6-: 802 if (done_i) -7-: 814 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -8-: 816 if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage)) -9-: 830 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)) -10-: 839 if (done_i) -11-: 851 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)) -12-: 857 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StRmaIdle 1 - - - - - - - - - - Covered T2,T3,T6
StRmaIdle 0 1 - - - - - - - - - Covered T2,T3,T84
StRmaIdle 0 0 - - - - - - - - - Covered T1,T2,T3
StRmaPageSel - - 1 - - - - - - - - Covered T14,T15
StRmaPageSel - - 0 1 - - - - - - - Covered T2,T3,T84
StRmaPageSel - - 0 0 - - - - - - - Covered T2,T84,T149
StRmaErase - - - - 1 - - - - - - Covered T2,T3,T84
StRmaErase - - - - 0 - - - - - - Covered T2,T3,T84
StRmaEraseWait - - - - - - - - - - - Covered T2,T3,T84
StRmaWordSel - - - - - 1 - - - - - Covered T2,T3,T84
StRmaWordSel - - - - - 0 1 - - - - Covered T2,T84,T149
StRmaWordSel - - - - - 0 0 - - - - Covered T2,T84,T149
StRmaProgram - - - - - - - 1 - - - Covered T2,T84,T149
StRmaProgram - - - - - - - 0 - - - Covered T2,T84,T149
StRmaProgramWait - - - - - - - - 1 - - Covered T2,T84,T149
StRmaProgramWait - - - - - - - - 0 - - Covered T2,T84,T149
StRmaRdVerify - - - - - - - - - 1 - Covered T2,T84,T149
StRmaRdVerify - - - - - - - - - 0 - Covered T2,T84,T149
StRmaRdVerify - - - - - - - - - - 1 Covered T2,T84,T149
StRmaRdVerify - - - - - - - - - - 0 Covered T2,T84,T149
StRmaDisabled - - - - - - - - - - - Covered T2,T3,T6
StRmaInvalid - - - - - - - - - - - Covered T17,T18,T19
default - - - - - - - - - - - Covered T17,T18,T19


Assert Coverage for Module : flash_ctrl_lcmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisableChk_A 400403896 6853849 0 45
ProgRdVerify_A 396761661 2043544 0 0
u_rma_state_regs_A 412561729 411800772 0 0
u_state_regs_A 412561729 411800772 0 0


DisableChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 400403896 6853849 0 45
T2 400434 10 0 0
T3 3393 20 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 520 0 1
T8 45438 0 0 0
T10 14232 0 0 0
T20 1100 0 0 0
T21 944 0 0 0
T27 0 152 0 1
T28 0 0 0 1
T31 0 0 0 1
T35 1236 3 0 0
T73 0 11 0 0
T80 0 0 0 1
T84 0 10 0 0
T85 0 11 0 0
T159 0 10 0 0
T171 0 21 0 0
T172 0 0 0 1
T173 0 0 0 1
T174 0 0 0 1
T175 0 0 0 1
T176 0 0 0 1

ProgRdVerify_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396761661 2043544 0 0
T2 400413 65920 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 0 0 0
T6 1053 0 0 0
T8 45438 0 0 0
T10 14232 0 0 0
T20 1100 0 0 0
T21 944 0 0 0
T35 1236 0 0 0
T84 0 65920 0 0
T101 0 4 0 0
T149 0 65920 0 0
T170 0 4 0 0
T177 0 65920 0 0
T178 0 65920 0 0
T179 0 65920 0 0
T180 0 65920 0 0
T181 0 65920 0 0

u_rma_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561729 411800772 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561729 411800772 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%