SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg_core.u_chk | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.86 | 100.00 | 99.43 | 100.00 | 100.00 | u_reg_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_chk | 100.00 | 100.00 | |||||
u_tlul_data_integ_dec | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.98 | 100.00 | 83.62 | 96.30 | 100.00 | u_tl_adapter_eflash |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_chk | 100.00 | 100.00 | |||||
u_tlul_data_integ_dec | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_reg_top |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_chk | 100.00 | 100.00 | |||||
u_tlul_data_integ_dec | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 22 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
22 | 1 | 1 | |
44 | unreachable | ||
49 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 3570 | 3570 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3570 | 3570 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T48 | 2 | 2 | 0 | 0 |
T49 | 2 | 2 | 0 | 0 |
T51 | 2 | 2 | 0 | 0 |
T52 | 2 | 2 | 0 | 0 |
T53 | 2 | 2 | 0 | 0 |
T54 | 2 | 2 | 0 | 0 |
T55 | 2 | 2 | 0 | 0 |
T56 | 2 | 2 | 0 | 0 |
T57 | 2 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 22 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
22 | 1 | 1 | |
44 | unreachable | ||
49 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 1259 | 1259 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1259 | 1259 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
T52 | 1 | 1 | 0 | 0 |
T53 | 1 | 1 | 0 | 0 |
T54 | 1 | 1 | 0 | 0 |
T55 | 1 | 1 | 0 | 0 |
T56 | 1 | 1 | 0 | 0 |
T57 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 22 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
22 | 1 | 1 | |
44 | unreachable | ||
49 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 1052 | 1052 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 22 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 0 | 0 | |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
22 | 1 | 1 | |
44 | unreachable | ||
49 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 1259 | 1259 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1259 | 1259 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
T52 | 1 | 1 | 0 | 0 |
T53 | 1 | 1 | 0 | 0 |
T54 | 1 | 1 | 0 | 0 |
T55 | 1 | 1 | 0 | 0 |
T56 | 1 | 1 | 0 | 0 |
T57 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |