Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Covered | T61,T66,T67 |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Covered | T61,T66,T67 |
1 | 1 | Covered | T61,T66,T67 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T61,T66,T67 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Covered | T11,T12,T13 |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Covered | T11,T13,T278 |
1 | 1 | Covered | T11,T12,T13 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T11,T12,T13 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Covered | T22,T26,T185 |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Covered | T22,T185,T316 |
1 | 1 | Covered | T22,T26,T185 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T22,T26,T185 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Covered | T183,T184,T189 |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Covered | T183,T184,T189 |
1 | 1 | Covered | T183,T184,T189 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T183,T184,T189 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 6 | 60.00 |
Logical | 10 | 6 | 60.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Not Covered | |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_macro_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_core.u_err_code_macro_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 6 | 60.00 |
Logical | 10 | 6 | 60.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T48,T49 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T48,T49,T50 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T48,T49 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Not Covered | |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T16,T48,T49 |
1 | Covered | T48,T49,T50 |
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_reg_intg_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_prog_intg_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_lcmgr_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Instance : tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
0 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |