Unified Coverage Report :: Module :: tlul_rsp_intg_gen

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	90.83					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen	90.00	80.00					100.00
tb.dut.u_to_prog_fifo.u_rsp_gen	91.67	83.33					100.00
tb.dut.u_to_rd_fifo.u_rsp_gen	91.67	83.33					100.00
tb.dut.u_reg_core.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen	100.00	100.00					100.00
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen	100.00	100.00					100.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen	100.00	100.00					100.00
tb.dut.u_tl_adapter_eflash.u_rsp_gen	100.00	100.00					100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	80.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	92.86					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.96	100.00	91.84			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.54	93.44	65.77			69.23	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.49	95.38	77.39			85.19	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.88	100.00	99.51			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.80	76.92	40.91			55.56		gen_err_resp.err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.73	96.15	77.27			77.78		u_tlul_err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.52	96.15	72.73			66.67		u_tlul_err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.93	96.92	81.90			88.89	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg_top

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.00	80.00

tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	32	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
91.67	83.33

tb.dut.u_to_prog_fifo.u_rsp_gen

SCORE	LINE
91.67	83.33

tb.dut.u_to_rd_fifo.u_rsp_gen

SCORE	LINE
83.33	66.67

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	9835	9835	0	0
PayLoadWidthCheck	9835	9835	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9835	9835	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T17	5	5	0	0
T22	5	5	0	0
T23	5	5	0	0
T60	5	5	0	0
T61	5	5	0	0
T63	5	5	0	0
T64	5	5	0	0
T65	5	5	0	0
T66	5	5	0	0
T67	5	5	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	9835	9835	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T17	5	5	0	0
T22	5	5	0	0
T23	5	5	0	0
T60	5	5	0	0
T61	5	5	0	0
T63	5	5	0	0
T64	5	5	0	0
T65	5	5	0	0
T66	5	5	0	0
T67	5	5	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1091	1091	0	0
PayLoadWidthCheck	1091	1091	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	32	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1091	1091	0	0
PayLoadWidthCheck	1091	1091	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	876	876	0	0
PayLoadWidthCheck	876	876	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	876	876	0	0
PayLoadWidthCheck	876	876	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1091	1091	0	0
PayLoadWidthCheck	1091	1091	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1091	1091	0	0
PayLoadWidthCheck	1091	1091	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	876	876	0	0
PayLoadWidthCheck	876	876	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	876	876	0	0
PayLoadWidthCheck	876	876	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
43	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	876	876	0	0
PayLoadWidthCheck	876	876	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1091	1091	0	0
PayLoadWidthCheck	1091	1091	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0